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precision analog microcontroller, 12-bit analog i/o, large memory, arm7tdmi mcu with enhanced irq handler data sheet aduc7124/aduc7126 rev. d document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2010C2014 analog devices, inc. all rights reserved. technical support www.analog.com features analog input/output multichannel, 12-bit, 1 msps adc up to 16 adc channels fully differential and single-ended modes 0 v to v ref analog input range 12-bit voltage output dacs 4 dac outputs available on-chip voltage reference on-chip temperature sensor (3c) voltage comparator microcontroller arm7tdmi core, 16-bit/32-bit risc architecture jtag port supports code download and debug clocking options trimmed on-chip oscillator (3%) external watch crystal external clock source up to 41.78 mhz 41.78 mhz pll with programmable divider memory 126 kb flash/ee memory, 32 kb sram in-circuit download, jtag-based debug software-triggered in-circuit reprogrammability vectored interrupt controller for fiq and irq 8 priority levels for each interrupt type interrupt on edge or level external pin inputs on-chip peripherals 2 fully i 2 c-compatible channels spi (20 mbps in master mode, 10 mbps in slave mode) with 4-byte fifo on input and output stages 2 uart channels with 16-byte fifo on input and output stages up to 40 gpio port all gpios are 5 v tolerant 4 general-purpose timers watchdog timer (wdt) and wake-up timer programmable logic array (pla) 16 pla elements 16-bit, 6-channel pwm power supply monitor power specified for 3 v operation active mode: 11.6 ma at 5 mhz, 33.3 ma at 41.78 mhz packages and temperature range fully specified for ?40c to +125c operation 64-lead lfcsp ( aduc7124 ) and 80-lead lqfp ( aduc7126 ) tools low cost quickstart development system full third-party support applications industrial control and automation systems smart sensors, precision instrumentation base station systems, optical networking patient monitoring functional block diagram 1msps 12-bit adc dac0 dac1 dac2 dac3 pwm external memory interface aduc7124/aduc7126 adc0 xclki xclko rst v ref adc15 mux temp sensor band gap ref osc and pll psm por cmp0 cmp1 cmp out pla vectored interrupt controller 4 general- purpose timers 8k 32 sram 63k 16 flash/ eeprom spi, 2 i 2 c, 2 uart gpio jtag arm7tdmi-based mcu with additional peripherals 09123-001 12-bit dac 12-bit dac 12-bit dac 12-bit dac figure 1.
aduc7124/aduc7126 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 general description ......................................................................... 5 specifications ..................................................................................... 6 timing specifications .................................................................. 9 absolute maximum ratings .......................................................... 14 esd caution ................................................................................ 14 pin configurations and function descriptions ......................... 15 typical performance characteristics ........................................... 24 terminology .................................................................................... 27 adc specifications .................................................................... 27 dac specifications ..................................................................... 27 overview of the arm7tdmi core ............................................. 28 thumb mode (t) ........................................................................ 28 long multiply (m) ...................................................................... 28 embeddedice (i) ....................................................................... 28 exceptions ................................................................................... 28 arm registers ............................................................................ 28 interrupt latency ........................................................................ 29 memory organization ................................................................... 30 memory access ........................................................................... 30 flash/ee memory ....................................................................... 30 sram ........................................................................................... 30 memory mapped registers ....................................................... 30 adc circuit overview .................................................................. 38 transfer function ....................................................................... 38 typical operation ....................................................................... 39 mmrs interface .......................................................................... 39 converter operation .................................................................. 41 driving the analog inputs ........................................................ 43 calibration ................................................................................... 44 temperature sensor ................................................................... 44 band gap reference ................................................................... 45 nonvolatile flash/ee memory ..................................................... 46 programming .............................................................................. 46 flash/ee memory security ....................................................... 47 flash/ee control interface ....................................................... 47 execution time from sram and flash/ee ............................ 50 reset and remap ........................................................................ 50 other analog peripherals .............................................................. 53 dac .............................................................................................. 53 power supply monitor ............................................................... 55 comparator ................................................................................. 55 oscillator and pll power control ........................................ 56 digital peripheral ........................................................................... 60 general - purpose input/output ................................................ 60 serial port mux ........................................................................... 62 uart serial interface ................................................................ 62 serial peripheral interface ......................................................... 68 i 2 c ................................................................................................. 72 pwm general overview ........................................................... 80 programmable logic array (pla) ........................................... 83 processor reference peripherals ................................................... 86 interrupt system ......................................................................... 86 irq ............................................................................................... 86 fast interrupt request (fiq) .................................................... 87 vectored interrupt controller (vic) ....................................... 88 timers .......................................................................................... 93 external memory interfacing ................................................... 99 hardware design considerations .............................................. 103 power supplies .......................................................................... 103 grounding and board layout recommendations ............... 104 clock oscillator ........................................................................ 104 power - on reset operation ..................................................... 105 outline dimensions ..................................................................... 106 ordering guide ........................................................................ 107 rev. d | page 2 o f 110
data sheet aduc7124/aduc7126 revision history 10 /14 rev. c to rev. d change conv start to c on v start ............................................................. universal changes to features section ............................................................ 1 changes to pin 17 and pin 30 descriptions ; t a b le 1 0 ................ 1 9 changes to flash/ee memory section and sram section ....... 3 0 changes to t a b le 1 3 ........................................................................ 3 2 changes to flash/ee memory section , programming section, and s erial downloading (in - circuit programming) section ... 4 6 changes to flash/ee memory security section .......................... 4 7 changes to t a b le 56 and t a b le 57 ................................................. 5 0 changes to t a b le 6 9 ........................................................................ 5 6 changes to t a b le 78 ........................................................................ 6 0 changes to i 2 c section ................................................................... 7 2 update t a b le 1 02 ............................................................................. 7 3 update t a b le 109 ............................................................................. 7 6 chan ges to t a b le 1 1 0 ...................................................................... 7 7 changes to t1cap register .......................................................... 9 6 5 /12 rev . b to rev . c changed bit to byte in gen eral description section .................... 4 changes to table 2 and table 3 ....................................................... 8 chan ges to table 4 and to figure 2 and figure 3 .......................... 9 changes to table 5 and figure 4 .................................................... 10 changes to table 6 and figure 5 .................................................... 11 changes table 7 and figure 6 ........................................................ 1 2 changes to pin 50 and pin 51 in table 9 ...................................... 14 chan g es to serial downloading (in - circuit programming) s ection ............................................................................................... 44 changes to table 77 ........................................................................ 59 change s to table 78 ........................................................................ 5 8 changes to t able 90 ........................................................................ 60 changes to normal 450 uart baud rate generation secti on ............................................................................................... 6 1 changes to s erial peripheral interface s ection ........................... 66 add e d euation to timer s section and added hr: min: s ec 1/128 format section ...................................................................... 91 changes to f igure 69 ................................................................... 103 updated outline dimensions ..................................................... 104 changes to ordering g uide ........................................................ 105 1 /1 1 rev a to rev b change s to tab le 1 ............................................................................ 5 10/10 rev. 0 to rev. a added aduc7126 .............................................................. universal changes to features section ............................................................ 1 moved figure 1 .................................................................................. 1 changes to figure 1 ........................................................................... 1 changes to general description section ....................................... 4 changes to voltage output at 25c, voltage tc, iov dd current in active mode, and iov dd curr ent in pause mode parameters, table 1 ................................................................................................. 5 change to table 8 ............................................................................ 13 changed refgnd to gnd ref ...................................................... 13 changes to figure 7 and table 9 ................................................... 14 added figure 8 and table 10; renumbered seuentially .......... 18 change to figure 17 caption ......................................................... 25 change to memory mapped registers section ........................... 29 change to figure 26 ........................................................................ 30 changes to table 18 ........................................................................ 32 changes to table 21 ........................................................................ 33 changes to table 22 ........................................................................ 34 moved table 25 ................................................................................ 35 change to table 25 .......................................................................... 35 added table 26 ................................................................................ 35 change to table 27 .......................................................................... 36 changes to temperature sensor section ..................................... 42 deleted table 59; renumbered seuentially ............................... 4 3 added downloading (in - circuit programming) via i 2 c section .......................................................................................... 44 change to tag access section and table 37 ............................. 45 changes to table 45 ........................................................................ 46 changes to rstcfg register section .......................................... 49 deleted table 72 and table 75 ....................................................... 49 deleted table 78 .............................................................................. 50 changes to dac section, table 6 2, and table 64 ....................... 51 changes to references to adc and the dacs setion, table 66, configuring dac buffers in op amp mode section, dacbcfg register section, and table 67 .................................. 52 added dacbkey1 register section and dacbkey2 register section .............................................................................................. 53 changes to table 69 an d figure 45 ............................................... 54 changes to and external crystal selection and external clock selection ........................................................................................... 55 changes to pllcon register and powcon0 register section .............................................................................................. 56 changes to table 78 ........................................................................ 58 changes to table 81 ........................................................................ 59 changes to table 84 and table 90 ................................................. 60 changes to table 93, com0 fcr register section, com1fcr register section, and table 94 ....................................................... 63 changes to serial peripheral interface section ........................... 66 change to spi registers section .................................................... 67 changes to spidiv register section and table 101 .................. 68 change to i 2 c master transmit register section ....................... 73 chang e to table 109 ........................................................................ 74 change to i 2 c slave status registers section ............................... 75 change to table 113 ........................................................................ 79 changes to table 114 title and figure 50 .................................... 80 change to irqclre register register ....................................... 90 change to figure 54 ........................................................................ 92 changes to table 141, t1clri register section, and t1cap reg ister section ............................................................................... 93 changes to table 143 ...................................................................... 94 added external memory interfacting section, table 145, table 146, and figure 57 ................................................................. 96 rev. d | page 3 of 110
aduc7124/aduc7126 data sheet added xmcfg register section, table 147, table 148, table 149, and table 150 ................................................................ 97 added figure 58 and figure 59 ..................................................... 98 added figure 60 a nd figure 61 ..................................................... 99 changes to figure 62 to figure 65 .............................................. 100 changes to figure 67 and figure 68 ........................................... 101 change to power - on reset operation section and figure 69 ........................................................................................ 102 added figure 71 ........................................................................... 103 changes to ordering guide ........................................................ 104 9/10 revision 0: initial version rev. d | page 4 o f 110
data sheet aduc7124/aduc7126 general descripti on the aduc7124 / aduc7126 are fully integrated, 1 msps, 12- bit data acquisition system incorporating high performance multichannel adcs, 16 - bit/32 - bit mcus, and flash/ee memory on a single chip. the adc consists of up to 12 single - ended inputs. an additional four inputs are available but are multiplexed with the four dac output pins. the adc can operate in single - ended or differen - tial input mode. the adc input voltage range is 0 v to vref. a low drift band gap reference, temperatur e sensor, and voltage comparator complete the adc peripheral set. the dac output range is programmable to one of three voltage ranges. the dac outputs have an enhanced feature of being able to retain their output voltage during a watchdog or soft - ware rese t sequence. the devices operate from an on - chip oscillator and a pll generating an internal high frequency clock of 41.78 mhz. this clock is routed through a programmable clock divider from which the mcu core clock operating frequency is generated. the mi crocontroller core is an arm7tdmi?, 16- bit/32 - bit risc machine, which offers up to 41 mips of peak perf ormance. thirty - two kilobytes of sram and 126 kb of nonvolatile flash/ee memory are provided on - chip. the arm7tdmi core views all memory and registers as a single linear array. the aduc7124 / aduc7126 contain an advanced interrupt controller. the vectored interrupt co ntroller (vic) allows every interrupt to be assigned a priority level. it also supports nested interrupts to a maximum level of eight per irq and fiq. when irq and fiq interrupt sources are combined, a total of 16 nested interrupt levels are supported. on - chip factory firmware supports in - circuit download via the uart serial interface port or the i 2 c port, while nonintrusive emulation is also supported via the jtag interface. these fea - tures are incorporated into a low cost quickstart? development system su pporting this microconverter? family. the parts contain a 16 - bit pwm with six output signals. for communication purposes, the parts contain 2 i 2 c channels that can be individually configured for master or slave mode. an spi interface supporting both maste r and slave modes is also provided. thirdly, 2 uart channels are provided. each uart contains a configurable 16 - b yte fifo with receive and transmit buffers. the parts operate from 2.7 v to 3.6 v and is specified over an industrial temperature range of ?40 c to +125c. when operat - ing at 41.78 mhz, the power dissipation is typically 120 m w. the aduc7124 is available in a 64 - lead lfcsp package. the aduc7126 is available in a 80 - lead lqfp package. rev. d | page 5 of 110
aduc7124/aduc7126 data sheet specifications av dd = iov dd = 2.7 v to 3.6 v, v ref = 2.5 v internal reference, f core = 41.78 mhz, t a = ?40c to +125c, unless otherwise noted. table 1 . parameter min typ max unit test conditions/comments adc channel specifications eight acquisition clocks and f adc /2 adc power - up time 5 s dc accuracy 1 , 2 resolutio n 12 bits integral nonlinearity 0.6 1.5 lsb 2.5 v internal reference 1.0 lsb 1.0 v external reference differential nonlinearity 3 , 4 0.5 +1/?0.9 lsb 2.5 v internal reference +0.7/?0.6 lsb 1.0 v external reference dc code distribution 1 lsb adc input is a dc voltage endpoint errors 5 offset error 1 2 lsb offset error match 1 lsb gain error 2 lsb gain error match 1 lsb dynamic performance in 1 h sine wae, sample 1 msps signal -to - noise ratio snr 6 db includes distortion and noise comonents total harmonic distortion thd 7 db pea harmonic or surious noise 7 db channel - to - channel crosstal db measured on adacent channels inut channels not eing samled hae a 2 h sine wae connected to them analog input inut voltage ranges 4 dierential mode v cm 6 v ref /2 v single - ended mode to v ref v leaage current 1 6 a inut caacitance 24 f during adc acuisition on - chip voltage reference 47 f rom v ref to agnd outut vo ltage 2 v accuracy mv t a 2c reerence temerature coeicient 1 m/c power suly reection ratio db outut imedance 4 t a 2c internal v ref power - on time 1 ms external reference input inut voltage range 62 av dd v dac channel specifications r l , c l 1 f dc accuracy 7 resolution 12 bits relatie accuracy 2 lsb dierential nonlinearity 1 lsb guaranteed monotonic oset error 1 mv 2 v internal reerence gain error 1 gain error mismatch 1 o ull scale on dac re d page 6 o 11
data sheet aduc7124/aduc7126 parameter min typ max unit test conditions/comments analog outputs output voltage range 0 0 to dac ref v dac ref range: dacgnd to dacv d d output voltage range 1 0 to 2.5 v output voltage range 2 0 to dacv dd v output impedance 0.5 ? dac in op amp mode dac output buffer in op amp mode input offset voltage 0.4 mv input offset voltage drift 4 v/c input offset current 2 na input bias current 2.5 na gain 70 db 5 k? load unity gain frequency 4.5 mhz r l = 5 k?, c l = 100 pf cmrr 78 db settling time 12 s r l = 5 k?, c l = 100 pf output slew rate 3.2 v/ s r l = 5 k?, c l = 100 pf psrr 75 db dac ac characteristics voltage output settling time 10 s digital -to - analog glitch energy 10 nv - sec 1 lsb change at major carry (where maximum number of bits simultaneously change in the dacxdat register) comparator input offset voltage 15 mv input bias current 1 a input voltage range agnd av dd C 1.2 v input capacitance 8.5 pf hysteresis 4 , 6 2 15 mv hysteresis can be turned on or off via the cmphyst bit in the cmpcon register response time 4 s 100 mv overdrive and configured with cmpres = 11 temperature sensor voltage output at 25c 1.415 v aduc7124 1.392 v aduc712 6 voltage temperature coefficient 3.914 mv/c aduc7124 4.52 mv/c aduc7126 accuracy 3 c a single poin t calibration is required ja thermal impedance 64- lead lfcsp 24 c/w power supply monitor (psm) iov dd trip point selection 2.79 v two selectable trip points 3.07 v power supply trip point accuracy 2.5 % of the selected nominal trip point voltage power - on reset 2.41 v watchdog timer (wdt) timeout period 0 512 sec flash/ee memory endurance 9 10,000 cycles data retention 10 20 years t j = 85c digital inputs all digital inputs excluding xclki and xclko logic 1 input current 0.2 1 a v ih = v dd or v ih = 5 v logic 0 input current ?40 ?60 a v il = 0 v; except tdi, tdo, and rtck ?80 ?120 a v il = 0 v; tdi, tdo, and rtck input capacitance 5 pf rev. d | page 7 of 110
aduc7124/aduc7126 data sheet parameter min typ max unit test conditions/comments logic inputs 3 all logic inputs excluding xclki v inl , input low voltage 0.8 v v inh , input high voltage 2.0 v logic outputs all digital outputs excluding xclko v oh , output high voltage 2.4 v i source = 1.6 m a v ol , output low voltage 11 0.4 v i sink = 1.6 ma crystal inputs xclki and xclko logic inputs, xclki o nly v inl , input low voltage 0.8 v v inh , input high voltage 1.6 v xclki input capacitance 20 pf xclko output capacitance 20 pf internal oscillator 32.768 khz 3 % mcu clock rate 4 from 32 khz internal oscillator 326 khz cd = 7 from 32 khz external crystal 41.78 mhz cd = 0 using an external clock 0.05 44 mhz t a = 85c 0.05 41.78 mhz t a = 125c start - up time core clock = 41.78 mhz at power - on 66 ms from pause/nap mode 2.6 s cd = 0 247 s cd = 7 from sleep mode 1.58 ms from stop mode 1.7 ms programmable logic array (pla) pin propagation delay 12 ns from input pin to output pin element propagation delay 2.5 ns power requirements 12, 13 power supply voltage range av dd to agnd and iov dd to iognd 2.7 3.6 v analog power supply currents av dd current 165 a adc in idle mode dacv dd current 14 0.02 a digital power supply current iov dd current in active mode code executing from flash/ee 8.1 12.5 ma cd = 7 11.6 17 ma cd = 3 33.3 50 ma cd = 0 (41.78 mhz clock) iov dd current in pause mode 20.6 30 m a cd = 0 (41.78 mhz clock) iov dd current in sleep mode 110 a t a = 85c 600 680 a t a = 125c additional power supply currents adc 1.26 ma at 1 msps 0.7 ma at 62.5 ksps dac 315 a per dac rev. d page 8 o f 110
data sheet aduc7124/aduc7126 parameter min typ max unit test conditions/comments esd tests 2.5 v reference, t a = 25c hbm passed up to 3 kv ficdm passed up to 1.5 kv 1 all adc channel specifications are guaranteed during normal core operation. 2 apply to all adc input chan nels. 3 measured using the factory - set default values in the adc offset register (adcof) and gain coefficient register (adcgn) . 4 not production tested but supported by design and/or characterization data on production release. 5 measured using the factory - set default values in adcof and adcgn with an external ad845 op amp as an input buffer stage as shown in figure 37 . based on external adc system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the calibration section). 6 the input signal can be centered on any dc common - mode voltage ( v cm ) as long as this value is within the ad c voltage input range specified. 7 dac linearity is calculated using a reduced code range of 100 to 3995. 8 dac gain error is calculated using a reduced code range of 100 to internal 2.5 v v ref . 9 endurance is qualified as per jedec standard 22 method a117 and measured at ?40c, +25c, +85c, and +125c. 10 retention lifetime equivalent at junction temperature (t j ) = 85c as per jedec standard 22 method a117. retention lifetime derates with junction temperature. 11 test carried out with a maximum of eight i/o s set to a low output level. 12 power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode wi th 3.6 v supply , pause mode with 3.6 v supply , and sleep mode with 3.6 v supply. 13 iov dd power suppl y current increases typically by 2 ma during a flash/ee erase cycle. 14 t his current must be added to the av dd current. timing specification s i 2 c timing table 2 i 2 c timing in fast mode (00 kh) slave master parameter description min max typ unit t l scl low pulse width 200 1360 ns t h scl high pulse width 100 1140 ns t shd start condition hold time 300 ns t dsu data setup time 1 00 740 ns t dhd data hold time 0 400 ns t rsu setup time for repeated start 100 ns t psu stop condition setup time 100 800 ns t buf bus - free time between a stop condition and a start condition 1.3 s t r rise time for both scl and sda 300 200 ns t f fall time for both scl and sda 300 ns table 3 . i 2 c timing in standard mode (100 khz) slave parameter description min max unit t l scl low pulse width 4.7 s t h scl high pulse width 4.0 ns t shd start condition hold time 4.0 s t dsu data setup time 250 ns t dhd data hold time 0 3.45 s t rsu setup time for repeated start 4.7 s t psu stop condition setup time 4.0 s t buf bus - free time between a stop condition and a start condition 4.7 s t r rise time for both scl a nd sda 1 s t f fall time for both scl and sda 300 ns rev. d | page 9 of 110
aduc7124/aduc7126 data sheet rev. d | page 10 of 110 sda (i/o) t buf msb lsb ack msb 1 9 8 2?7 1 scl (i) ps stop condition start condition s(r) repeated start t r t f t f t r t h t l t dsu t dhd t rsu t dhd t dsu t shd t psu 0 9123-029 figure 2. i 2 c-compatible in terface timing spi timing table 4. spi master mode timing (phase mode = 1) parameter description min typ max unit t sl sclk low pulse width 1 (spidiv + 1) t uclk ns t sh sclk high pulse width 1 (spidiv + 1) t uclk ns t dav data output valid after sclk edge 25 ns t dsu data input setup time before sclk edge 1 1 t uclk ns t dhd data input hold time after sclk edge 1 2 t uclk ns t df data output fall time 5 12.5 ns t dr data output rise time 5 12.5 ns t sr sclk rise time 5 12.5 ns t sf sclk fall time 5 12.5 ns 1 t uclk = 23.9 ns. it corresponds to the 41.78 mhz internal clock from the pll before the clock divider. 0 9123-030 sclk (polarity = 0) sclk (polarity = 1) mosi msb bit 6 to bit 1 lsb miso msb in bit 6 to bit 1 lsb in t sh t sl t sr t sf t dr t df t dav t dsu t dhd figure 3. spi master mode timing (phase mode = 1)
data sheet aduc7124/aduc7126 rev. d | page 11 of 110 table 5. spi master mode timing (phase mode = 0) parameter description min typ max unit t sl sclk low pulse width 1 (spidiv + 1) t uclk ns t sh sclk high pulse width 1 (spidiv + 1) t uclk ns t dav data output valid after sclk edge 25 ns t dosu data output setup before sclk edge 75 ns t dsu data input setup time before sclk edge 1 1 t uclk ns t dhd data input hold time after sclk edge 1 2 t uclk ns t df data output fall time 5 12.5 ns t dr data output rise time 5 12.5 ns t sr sclk rise time 5 12.5 ns t sf sclk fall time 5 12.5 ns 1 t uclk = 23.9 ns. it corresponds to the 41.78 mhz internal clock from the pll before the clock divider. 09123-031 sclk (polarity = 0) sclk (polarity = 1) t sh t sl t sr t sf mosi msb bit 6 to bit 1 lsb miso msb in bit 6 to bit 1 lsb in t dr t df t dav t dosu t dsu t dhd figure 4. spi master mode timing (phase mode = 0)
aduc7124/aduc7126 data sheet rev. d | page 12 of 110 table 6. spi slave mode timing (phase mode = 1) parameter description min typ max unit t cs cs to sclk edge 200 ns t sl sclk low pulse width (spidiv + 1) t hclk ns t sh sclk high pulse width (spidiv + 1) t hclk ns t dav data output valid after sclk edge 25 ns t dsu data input setup time before sclk edge 1 1 t uclk ns t dhd data input hold time after sclk edge 1 2 t uclk ns t df data output fall time 5 12.5 ns t dr data output rise time 5 12.5 ns t sr sclk rise time 5 12.5 ns t sf sclk fall time 5 12.5 ns t sfs cs high after sclk edge 0 ns 1 t uclk = 23.9 ns. it corresponds to the 41.78 mhz internal clock from the pll before the clock divider. 09123-132 sclk (polarity = 0) cs sclk (polarity = 1) t sh t sl t sr t sf t sfs miso msb bit 6 to bit 1 lsb mosi msb in bit 6 to bit 1 lsb in t dhd t dsu t dav t dr t df t cs figure 5. spi slave mode timing (phase mode = 1)
data sheet aduc7124/aduc7126 rev. d | page 13 of 110 table 7. spi slave mode timing (phase mode = 0) parameter description min typ max unit t cs cs to sclk edge 200 ns t sl sclk low pulse width (spidiv + 1) t hclk ns t sh sclk high pulse width (spidiv + 1) t hclk ns t dav data output valid after sclk edge 25 ns t dsu data input setup time before sclk edge 1 1 t uclk ns t dhd data input hold time after sclk edge 1 2 t uclk ns t df data output fall time 5 12.5 ns t dr data output rise time 5 12.5 ns t sr sclk rise time 5 12.5 ns t sf sclk fall time 5 12.5 ns t docs data output valid after cs edge 25 ns t sfs cs high after sclk edge 0 ns 1 t uclk = 23.9 ns. it corresponds to the 41.78 mhz internal clock from the pll before the clock divider. 09123-033 sclk (polarity = 0) cs sclk (polarity = 1) t sh t sl t sr t sf t sfs miso mosi msb in bit 6 to bit 1 lsb in t dhd t dsu msb bit 6 to bit 1 lsb t docs t dav t dr t df t cs figure 6. spi slave mode timing (phase mode = 0)
aduc7124/aduc7126 data sheet absolute maximum rat i ngs agnd = gnd ref = dacgnd = gnd ref , t a = 25c, unless otherwise noted. table 8 . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the o perational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating can be applied at any one time. esd caution parameter rating av dd to iov dd ?0.3 v to +0.3 v agnd to dgnd ?0.3 v to +0.3 v iov dd to iognd, av dd to agnd ?0.3 v to +6 v digital input voltage t o iognd ?0.3 v to +5.3 v digital output voltage to iognd ?0.3 v to iov dd + 0.3 v v ref to agnd ?0.3 v to av dd + 0.3 v analog inputs to agnd 0.3 v to av dd + 0.3 v analog outputs to agnd 0.3 v to av dd + 0.3 v operating temperature range, industrial ? 4 0c to +125c storage temperature range 65c to +150c junction temperature 150c ja thermal impedance 64- lead lfcsp 24 c/w 80- lead lqfp 38 c/w peak solder reflow temperature snpb assemblies (10 sec to 30 sec) 240c rohs compliant assemblies ( 20 sec to 40 sec) 260c rev. d | page 14 o f 110
data sheet aduc7124/aduc7126 pin configur ations and function descriptions pin 1 indic a t or 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 dgnd l v dd iov dd iognd p4.6/plao[14] p4.7/plao[15] p0.6/t1/mrst/plao[3] tck tdo p3.0/pwm0/plai[8] p3.1/pwm1/plai[9] p3.2/pwm2/plai[10] p3.3/pwm3/plai[ 1 1] p0.3/trst/adc bus y p3.4/pwm4/plai[12] p3.5/pwm5/plai[13] 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 adc3/cmp1 adc2/cmp0 adc1 adc0 gnd ref agnd a v dd dac ref v ref rtck p4.4/plao[12] p4.3/plao[ 1 1] p4.2/plao[10] p1.0/t1/spm0/sin0/i2c0scl/plai[0] p1.1/spm1/sout0/i2c0sda/plai[1] p1.2/spm2/rts/i2c1scl/plai[2] 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 adc4 adc5 adc6 adc7 adc8 adc9 adcneg dacgnd dacv dd dac0/adc12 dac1/adc13 tms tdi xclko xclki bm/p0.0/cmp out /plai[7] nc = no connect p1.3/spm3/cts/i2c1sda/plai[3] p1.4/spm4/ri/spiclk/plai[4]/irq2 p1.5/spm5/dcd/spimiso/plai[5]/irq3 p4.1/plao[9]/sout1 p4.0/plao[8]/sin1 p1.6/spm6/plai[6] p1.7/spm7/dtr/spics/plao[0] p3.7/pwm sync /plai[15] p3.6/pwm trip /plai[14] iov dd iognd p0.7/eclk/xclk/spm8/plao[4]/sin0 p2.0/spm9/plao[5]/conv st art /sout0 irq1/p0.5/adc busy /plao[2] irq0/p0.4/pwm trip /plao[1] rst 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 aduc7124 t op view (not to scale) 09123-107 notes 1. the exposed paddle must be soldered to the pcb to ensure proper heat dissipation, noise, and mechanical strength benefits. figure 7. aduc7124 pin configuration table 9 . pin function descriptions ( aduc7124 64- lead lfcsp) pin no. mnemonic description 0 exposed paddle exposed paddle. the lfcsp_vq has an exposed paddle that must be left unconnected. 1 adc4 single - ended or differential analog input 4. 2 adc 5 single - ended or differential analog input 5. 3 adc6 single - ended or differential analog input 6. 4 adc7 single - ended or differential analog input 7. 5 adc8 single - ended or differential analog input 8. 6 adc9 single - ended or differential analog input 9. 7 adcneg bias point or negative analog input of the adc in pseudo differential mode. must be connected to the ground of the signal to convert. this bias point must be between 0 v and 1 v. 8 dacgnd ground for the dac. typically connected to agnd. 9 d acv dd 3.3 v power supply for the da cs. must be connected to av dd . 10 dac0/adc12 dac0 voltage output (dac0). single - ended or differential analog input 12 (adc12). 11 dac1/adc13 dac1 voltage output (dac1). single - ended or differential analog input 13 (adc1 3). 12 tms jtag test port input, test mode select. debug and download access. 13 tdi jtag test port input, test data in. rev. d | page 15 of 110
aduc7124/aduc7126 data sheet rev. d | page 16 of 110 pin no. mnemonic description 14 xclko output from the crystal oscillator inverter. 15 xclki input to the crystal oscillator inverter and input to the internal clock generator circuits. 16 bm/p0.0/cmp out /plai[7] multifunction i/o pin. boot mode (bm). the aduc7124 enters download mode if bm is low at reset and executes code if bm is pulled high at reset through a 1 k resistor. general-purpose input and output port 0.0 (p0.0). voltage comparator output (cmp out ) programmable logic array in put element 7 (plai[7]). 17 dgnd ground for core logic. 18 lv dd 2.6 v output of the on-chip voltage regulato r. this output must be connected to a 0.47 f capacitor to dgnd only. 19 iov dd 3.3 v supply for gpio and input of the on-chip voltage regulator. 20 iognd ground for gpio. typically connected to dgnd. 21 p4.6/plao[14] general-purpose input and output port 4.6 (p4.6). programmable logic array output element 14 (plao[14]). 22 p4.7/plao[15] general-purpose input and output port 4.7 (p4.7). programmable logic array output element 15 (plao[15]). 23 p0.6/t1/mrst/plao[3] multifunction pin, driven low after reset. general-purpose output port 0.6 (p0.6). timer1 input (t1). power-on reset output (mrst). programmable logic array output element 3 (plao[3]). 24 tck jtag test port input, test clock. debug and download access. 25 tdo jtag test port output, test data out. 26 p3.0/pwm0/plai[8] general-purpose input and output port 3.0 (p3.0). pwm phase 0 (pwm0). programmable logic array input element 8 (plai[8]). 27 p3.1/pwm1/plai[9] general-purpose input and output port 3.1 (p3.1). pwm phase 1 (pwm1). programmable logic array in put element 9 (plai[9]). 28 p3.2/pwm2/plai[10] general-purpose input and output port 3.2 (p3.2). pwm phase 2 (pwm2). programmable logic array input element 10 (plai[10]). 29 p3.3/pwm3/plai[11] general-purpose input and output port 3.3 (p3.3). pwm phase 3 (pwm3). programmable logic array in put element 11 (plai[11]). 30 p0.3/trst/adc busy general-purpose input and output port 0.3 (p0.3). jtag test port input, test reset (trst). jtag reset input. debug and download access. if this pin is held low, jtag access is not possible because the jtag interface is held in reset and p0.1/p0.2/p0.3 are configured as gpio pins. adc busy signal output (adc busy ). 31 p3.4/pwm4/plai[12] general-purpose input and output port 3.4 (p3.4). pwm phase 4 (pwm4). programmable logic array input 12 (plai[12]). 32 p3.5/pwm5/plai[13] general-purpose input and output port 3.5 (p3.5). pwm phase 5 (pwm5). programmable logic array in put element 13 (plai[13]). 33 rst reset input, active low. 34 irq0/p0.4/pwm trip /plao[1] multifunction i/o pin. external interrupt request 0, active high (irq0). general-purpose input and output port 0.4 (p0.4). pwm trip external input (pwm trip ). programmable logic array output element 1 (plao[1]).
data sheet aduc7124/aduc7126 rev. d | page 17 of 110 pin no. mnemonic description 35 irq1/p0.5/adc busy /plao[2] multifunction i/o pin. external interrupt request 1, active high (irq1). general-purpose input and output port 0.5 (p0.5). adc busy signal output (adc busy ). programmable logic array output element 2 (plao[2]). 36 p2.0/spm9/plao[5]/conv start /sout0 general-purpose input and output port 2.0 (p2.0). serial port multiplexed (spm9). programmable logic array output element 5 (plao[5]). start conversion input signal for adc (conv start ). uart0 output (sout0). 37 p0.7/eclk/xclk/spm8/plao[4]/sin0 general-purpose input and output port 0.7 (p0.7). output for external clock signal (eclk). input to the internal clock generator circuits (xclk). serial port multiplexed (spm8). programmable logic array output element 4 (plao[4]). uart0 input (sin0). 38 iognd ground for gpio. typically connected to dgnd. 39 iov dd 3.3 v supply for gpio and input of the on-chip voltage regulator. 40 p3.6/pwm trip /plai[14] general-purpose input and output port 3.6 (p3.6). pwm safety cutoff (pwm trip ). programmable logic array in put element 14 (plai[14]). 41 p3.7/pwm sync /plai[15] general-purpose input and output port 3.7 (p3.7). pwm synchronization input/output (pwm sync ). programmable logic array input element 15 (plai[15]). 42 p1.7/spm7/dtr/spics /plao[0] general-purpose inp ut and output port 1.7 (p1.7). serial port multiplexed. uart, spi (spm7). data terminal ready (dtr). chip select (spics ). programmable logic array output element 0 (plao[0]). 43 p1.6/spm6/plai[6] general-purpose input and output port 1.6 (p1.6). serial port multiplexed (spm6). programmable logic array input element 6 (plai[6]). 44 p4.0/plao[8]/sin1 general-purpose input and output port 4.0 (p4.0). programmable logic array output element 8 (plao[8]). uart1 input (sin1). 45 p4.1/plao[9]/sout1 general-purpose input and output port 4.1 (p4.1). programmable logic array output element 9 (plao[9]). uart1 output (sout1). 46 p1.5/spm5/dcd/spimiso/plai[5]/irq3 general-purpose input and output port 1.5 (p1.5). serial port multiplexed. uart, spi (spm5). data carrier detect (dcd). master input, slave output (spi miso). programmable logic array input element 5 (plai[5]). external interrupt request 3, active high (irq3). 47 p1.4/spm4/ri/spiclk/plai[4]/irq2 general-purpose input and output port 1.4 (p1.4). serial port multiplexed. uart, spi (spm4). ring indicator (ri). serial clock input/output (spi sclk). programmable logic array input element 4 (plai[4]). external interrupt request 2, active high (irq2). 48 p1.3/spm3/cts/i2c1sda/plai[3] general-purpose input and output port 1.3 (p1.3). serial port multiplexed. uart, i2c1 (spm3). clear to send (cts). i2c1 (i2c1sda). programmable logic array input element 3 (plai[3]). 49 p1.2/spm2/rts/i2c1scl/plai[2] general-purpose input and output port 1.2 (p1.2). serial port multiplexed (spm2). ready to send (rts). i2c1 (i2c1scl). programmable logic array input element 2 (plai[2]).
aduc7124/aduc7126 data sheet rev. d | page 18 of 110 pin no. mnemonic description 50 p1.1/spm1/sout0/i2c0sda/plai[1] general-purpose input and output port 1.1 (p1.1). serial port multiplexed (spm1). uart download pin, uart0 output (sout0). i2c0 (i2c0sda). programmable logic array input element 1 (plai[1]). 51 p1.0/t1/spm0/sin0/i2c0scl/plai[0] general-purpose input and output port 1.0 (p1.0). timer1 input (t1). serial port multiplexed (spm0). uart download pin, uart0 input (sin0). i2c0 (i2c0scl). programmable logic array in put element 0 (plai[0]). 52 p4.2/plao[10] general-purpose input and output port 4.2 (p4.2). programmable logic array output element 10 (plao[10]). 53 p4.3/plao[11] general-purpose input and output port 4.3 (p4.3). programmable logic array output element 11 (plao[11]). 54 p4.4/plao[12] general-purpose input and output port 4.4 (p4.4). programmable logic array output element 12 (plao[12]). 55 rtck jtag test port output, jtag return test clock. 56 v ref 2.5 v internal voltage reference. must be connected to a 0.47 f capacitor when using the internal reference. 57 dac ref external voltage reference for the dacs. range: dacgnd to dacv dd . 58 av dd 3.3 v analog power. 59 agnd analog ground. ground reference point for the analog circuitry. 60 gnd ref ground voltage reference for the adc. for optimal performance, the analog power supply should be separated from iognd and dgnd. 61 adc0 single-ended or differential analog input 0. 62 adc1 single-ended or differential analog input 1. 63 adc2/cmp0 single-ended or differential analog input 2 (adc2). comparator positive input (cmp0). 64 adc3/cmp1 single-ended or differential analog input 3 (adc3). comparator negative input (cmp1).
data sheet aduc7124/aduc7126 2 adc5 3 adc6 4 adc7 7 adc10 6 adc9 5 adc8 1 adc4 8 adcneg 9 dacgnd 10 dacv dd 12 dac1/adc13 13 dac2/adc14 14 dac3/adc15 15 tms 16 tdi 17 p0.1/pwm4/ble 18 xclko 19 xclki 20 bm/p0.0/cmp out /plai[7]/ms0 1 1 dac0/adc12 59 58 57 54 55 56 60 53 52 p1.4/spm4/ri/spiclk/plai[4]/irq2 p1.5/spm5/dcd/spimiso/plai[5]/irq3 p4.1/spm 1 1/sout1/ad9/plao[9] p1.7/spm7/dtr/spics/plao[0] p1.6/spm6/plai[6] p4.0/spm10/sin1/ad8/plao[8] p1.3/spm3/cts/i2c1sda/plai[3] p3.7/ad7/pwm sync /plai[15] p3.6/ad6/pwm trip /plai[14] 51 p2.2/rs/pwm1/plao[7] 49 p2.3/spm12/ae/sin1 48 iov dd 47 iognd 46 p0.7/spm8/eclk/xclk/plao[4]/sin0 45 p2.0/spm9/plao[5]/conv st art /sout0 44 p2.7/pwm3/ms3 43 irq1/p0.5/adc busy /plao[2]/ms2 42 irq0/p0.4/pwm trip /plao[1]/ms1 41 rst 50 p2.1/ws/pwm0/plao[6] 21 dgnd 22 l v dd 23 iov dd 24 iognd 25 p4.6/ad14/plao[14] 26 p4.7/ad15/plao[15] 27 p0.6/t1/mrst/plao[3]/ms3 28 tck 29 tdo 30 p0.2/pwm5/bhe 31 p3.0/ad0/pwm0/plai[8] 32 p3.1/ad1/pwm1/plai[9] 33 p3.2/ad2/pwm2/plai[10] 34 p3.3/ad3/pwm3/plai[ 1 1] 35 p2.4/spm13/pwm0/ms0/sout1 36 p0.3/trst/a16/adc bus y 37 p2.5/pwm1/ms1 38 p2.6/pwm2/ms2 39 p3.4/ad4/pwm4/plai[12] 40 p3.5/ad5/pwm5/plai[13] 80 adc3/cmp1 79 adc2/cmp0 78 adc1 77 adc0 76 adc 1 1 75 gnd ref 74 agnd 73 agnd 72 a v dd 71 dac ref 70 v ref 69 iognd 68 iov dd 67 p4.5/ad13/plao[13]/rtck 66 p4.4/ad12/plao[12] 65 p4.3/ad 1 1/plao[ 1 1] 64 p4.2/ad10/plao[10] 63 p1.0/t1/spm0/sin0/i2c0scl/plai[0] 62 p1.1/spm1/sout0/i2c0sda/plai[1] 61 p1.2/spm2/rts/i2c1scl/plai[2] pin 1 top view 09123-108 aduc7126 figure 8. aduc7126 pin configuration table 10 . pin function descriptions ( aduc7126 80 - lead lqfp) pin no. mnem onic description 1 adc4 single - ended or differential analog input 4. 2 adc5 single - ended or differential analog input 5. 3 adc6 single - ended or differential analog input 6. 4 adc7 single - ended or differential analog input 7. 5 adc8 single - ended or dif ferential analog input 8. 6 adc9 single - ended or differential analog input 9. 7 adc10 single - ended or differential analog input 10. 8 adcneg bias point or negative analog input of the adc in pseudo differential mode. must be connected to the ground of t he signal to convert. this bias point must be between 0 v and 1 v. 9 dacgnd ground for the dac. typically connected to agnd. 10 dacv dd 3.3 v power supply for the dacs. must be connected to av dd . rev. d | page 19 of 110
aduc7124/aduc7126 data sheet rev. d | page 20 of 110 pin no. mnemonic description 11 dac0/adc12 dac0 voltage output (dac0). single-ended or differential analog input 12 (adc12). 12 dac1/adc13 dac1 voltage output (dac1). single-ended or differential analog input 13 (adc13). 13 dac2/adc14 dac2 voltage output (dac2). single-ended or differential analog input 14 (adc14). 14 dac3/adc15 dac3 voltage output (dac3). single-ended or differential analog input 15 (adc15). 15 tms jtag test port input, test mode select. debug and download access. 16 tdi jtag test port input, test data in. debug and download access. 17 p0.1/pwm4/ble general-purpose input and output port 0.1 (p0.1). pwm phase 4 (pwm4). external memory byte low enable (ble ). this pin does not work as gpio on i 2 c versions of the chip. 18 xclko output from the crystal oscillator inverter. 19 xclki input to the crystal oscillator inverter and input to the internal clock generator circuits. 20 bm/p0.0/cmp out /plai[7]/ms0 multifunction i/o pin. boot mode entry pin (bm). the aduc7126 enters uart download mode if bm is low at reset and executes code if bm is pulled high at reset through a 1 k resistor.. the aduc7126 enters i 2 c download mode in i 2 c version parts if bm is low at reset with a flash address of 0x800014 = 0xfffffffff. the aduc7126 executes code if bm is pulled high at reset or if bm is low at reset with a flash address 0x800014 0xfffffffff. general-purpose input and output port 0.0 (p0.0). voltage comparator output/programmable logic array input element 7 (cmp out ). external memory select 0 (ms0). by defa ult, this pin is configured as gpio. 21 dgnd ground for core logic. 22 lv dd 2.6 v output of the on-chip voltage regulator. this output must be connected to a 0.47 f capacitor to dgnd only. 23 iov dd 3.3 v supply for gpio and input of the on-chip voltage regulator. 24 iognd ground for gpio. typically connected to dgnd. 25 p4.6/ad14/plao[14] general-purpose input and output port 4.6 (p4.6). external memory interface (ad14). programmable logic array output element 14 (plao[14]). 26 p4.7/ad15/plao[15] general-purpose input and output port 4.7 (p4.7). external memory interface (ad15). programmable logic array output element 15 (plao[15]). 27 p0.6/t1/mrst/plao[3]/ms3 multifunction pin, driven low after reset. general-purpose output port 0.6 (p0.6). timer1 input (t1). power-on reset output (mrst). programmable logic array output element 3 (plao[3]). external memory select 3 (ms3). 28 tck jtag test port input, test clock. debug and download access. 29 tdo jtag test port output, test data out. debug and download access. 30 p0.2/pwm5/bhe general-purpose input and output port 0.2 (p0.2). pwm phase 5 (pwm5). external memory byte high enable (bhe ). this pin does not work as gpio on i 2 c versions of the chip. 31 p3.0/ad0/pwm0/plai[8] general-purpose input and output port 3.0 (p3.0). external memory interface (ad0). pwm phase 0 (pwm0). programmable logic array in put element 8 (plai[8]). 32 p3.1/ad1/pwm1/plai[9] general-purpose input and output port 3.1 (p3.1). external memory interface (ad1). pwm phase 1 (pwm1). programmable logic array in put element 9 (plai[9]).
data sheet aduc7124/aduc7126 rev. d | page 21 of 110 pin no. mnemonic description 33 p3.2/ad2/pwm2/plai[10] general-purpose input and output port 3.2 (p3.2). external memory interface (ad2). pwm phase 2 (pwm2). programmable logic array in put element 10 (plai[10]). 34 p3.3/ad3/pwm3/plai[11] general-purpose input and output port 3.3 (p3.3). external memory interface (ad3). pwm phase 3 (pwm3). programmable logic array in put element 11 (plai[11]). 35 p2.4/spm13/pwm0/ms0/sout1 general-purpose input and output port 2.4 (p2.4). serial port multiplexed (spm13) pwm phase 0 (pwm0). external memory select 0 (ms0). uart1 output (sout1). 36 p0.3/trst/a16/adc busy general-purpose input and output port 0.3 (p0.3). jtag test port input, test reset (trst).jtag reset input. debug and download access. if this pin is held low, jtag access is not pos sible because the jtag interface is held in reset and p0.1/p0.2/p0.3 are configured as gpio pins. address line (a16). adc busy signal output (adc busy ). 37 p2.5/pwm1/ms1 general-purpose input and output port 2.5 (p2.5). pwm phase 1 (pwm1). external memory select 1 (ms1). 38 p2.6/pwm2/ms2 general-purpose input and output port 2.6 (p2.6). pwm phase 2 (pwm2). external memory select 2 (ms2). 39 p3.4/ad4/pwm4/plai[12] general-purpose input and output port 3.4 (p3.4). external memory interface (ad4). pwm phase 4 (pwm4). programmable logic array input 12 (plai[12]). 40 p3.5/ad5/pwm5/plai[13] general-purpose input and output port 3.5 (p3.5). external memory interface (ad5). pwm phase 5 (pwm5). programmable logic array in put element 13 (plai[13]). 41 rst reset input, active low. 42 irq0/p0.4/pwm trip /plao[1]/ms1 multifunction i/o pin. external interrupt request 0, active high (irq0). general-purpose input and output port 0.4 (p0.4). pwm trip external input (pwm trip ). programmable logic array output element 1 (plao[1]). external memory select 1 (ms1).. 43 irq1/p0.5/adc busy /plao[2]/ms2 multifunction i/o pin. external interrupt request 1, active high (irq1). general-purpose input and output port 0.5 (p0.5). adc busy signal output (adc busy ). programmable logic array output element 2 (plao[2]). external memory select 2 (ms2). 44 p2.7/pwm3/ms3 general-purpose input and output port 2.7 (p2.7). pwm phase 3 (pwm3). external memory select 3 (ms3). 45 p2.0/spm9/plao[5]/conv start /sout0 general-purpose input and output port 2.0 (p2.0). serial port multiplexed (spm9). programmable logic array output element 5 (plao[5]). start conversion input signal for adc (conv start ). uart0 output (sout0). 46 p0.7/spm8/eclk/xclk/plao[4]/sin0 general-purpose input and output port 0.7 (p0.7). serial port multiplexed (spm8). output for external clock signal (eclk). input to the internal clock ge nerator circuits (xclk). programmable logic array output element 4 (plao[4]). uart0 input (sin0). 47 iognd ground for gpio. typically connected to dgnd.
aduc7124/aduc7126 data sheet rev. d | page 22 of 110 pin no. mnemonic description 48 iov dd 3.3 v supply for gpio and input of the on-chip voltage regulator. 49 p2.3/spm12/ae/sin1 general-purpose input and output port 2.3 (p2.3). serial port multiplexed (spm12). external memory access enable (ae). uart1 input (sin1). 50 p2.1/ws /pwm0/plao[6] general-purpose input and output port 2.1 (p2.1). external memory write strobe (ws ). pwm phase 0 (pwm0). programmable logic array output element 6 (plao[6]). 51 p2.2/rs /pwm1/plao[7] general-purpose input and output port 2.2 (p2.2). external memory read strobe (rs ). pwm phase 1 (pwm1). programmable logic array output element 7 (plao[7]). 52 p3.6/ad6/pwm trip /plai[14] general-purpose input and output port 3.6 (p3.6). external memory interface (ad6). pwm safety cutouff (pwm trip ). programmable logic array in put element 14 (plai[14]). 53 p3.7/ad7/pwm sync /plai[15] general-purpose input and output port 3.7 (p3.7). external memory interface (ad7). pwm synchronization (pwm sync ). programmable logic array in put element 15 (plai[15]). 54 p1.7/spm7/dtr/spics /plao[0] general-purpose input and output port 1.7 (p1.7). serial port multiplexed (spm7). data terminal ready (dtr). chip select (spics ). programmable logic array output element 0 (plao[0]). 55 p1.6/spm6/plai[6] general-purpose input and output port 1.6 (p1.6). serial port multiplexed (spm6). programmable logic array input element 6 (plai[6]). 56 p4.0/spm10/sin1/ad8/plao[8] general-purpose input and output port 4.0 (p4.0). serial port multiplexed (spm10). uart1 input (sin1). external memory interface (ad8). programmable logic array output element 8 (plao[8]). 57 p4.1/spm11/sout1/ad9/plao[9] general-purpose input and output port 4.1 (p4.1). serial port multiplexed (spm11). uart1 output (sout1). external memory interface (ad9). programmable logic array output element 9 (plao[9]). 58 p1.5/spm5/dcd/spimiso/plai[5]/irq3 general-purpose input and output port 1.5 (p1.5). serial port multiplexed (spm5). data carrier detect (dcd). master input, slave output (spi miso). programmable logic array input element 5 (plai[5]). external interrupt request 3, active high (irq3). 59 p1.4/spm4/ri/spiclk/plai[4]/irq2 general-purpose input and output port 1.4 (p1.4). serial port multiplexed (spm4). ring indicator (ri). serial clock input/output (spi sclk). programmable logic array input element 4 (plai[4]). external interrupt request 2, active high (irq2). 60 p1.3/spm3/cts/i2c1sda/plai[3] general-purpose input and output port 1.3 (p1.3). serial port multiplexed (spm3). clear to send (cts). i2c1 (i2c1sda). programmable logic array input element 3 (plai[3]). 61 p1.2/spm2/rts/i2c1scl/plai[2] general-purpose input and output port 1.2 (p1.2). serial port multiplexed (spm2). ready to send (rts). i2c1 (i2c1scl). programmable logic array input element 2 (plai[2]).
data sheet aduc7124/aduc7126 rev. d | page 23 of 110 pin no. mnemonic description 62 p1.1/spm1/sout0/i2c0sda/plai[1] general-purpose input and output port 1.1 (p1.1). serial port multiplexed (spm1). uart0 output (sout0). i2c0 (i2c0sda). programmable logic array input element 1 (plai[1]). 63 p1.0/t1/spm0/sin0/i2c0scl/plai[0] general-purpose input and output port 1.0 (p1.0). timer1 input (t1). serial port multiplexed (spm0). uart0 input (sin0). i2c0 (i2c0scl). programmable logic array in put element 0 (plai[0]). 64 p4.2/ad10/plao[10] general-purpose input and output port 4.2 (p4.2). external memory interface (ad10). programmable logic array output element 10 (plao[10]). 65 p4.3/ad11/plao[11] general-purpose input and output port 4.3 (p4.3). external memory interface (ad11). programmable logic array output element 11 (plao[11]). 66 p4.4/ad12/plao[12] general-purpose input and output port 4.4 (p4.4). external memory interface (ad12). programmable logic array output element 12 (plao[12]). 67 p4.5/ad13/plao[13]/rtck general-purpose input and output port 4.5 (p4.5). external memory interface (ad13). programmable logic array output element 13 (plao[13]). jtag return test clock (rtck). 68 iov dd 3.3 v supply for gpio and input of the on-chip voltage regulator. 69 iognd ground for gpio. typically connected to dgnd. 70 v ref 2.5 v internal voltage reference. must be connected to a 0.47 f capacitor when using the internal reference. 71 dac ref external voltage reference for the dacs. range: dacgnd to dacv dd . 72 av dd 3.3 v analog power. 73, 74 agnd analog ground. ground reference point for the analog circuitry. 75 gnd ref ground voltage reference for the adc. for optimal performance, the analog power supply should be separated from iognd and dgnd. 76 adc11 single-ended or differential analog input 11. 77 adc0 single-ended or differential analog input 0. 78 adc1 single-ended or differential analog input 1. 79 adc2/cmp0 single-ended or differential analog input 2 (adc2). comparator positive input (cmp0). 80 adc3/cmp1 single-ended or differential analog input 3 (adc3). comparator negative input (cmp1).
aduc7124/aduc7126 data sheet typical performance characteristics 0.3 0.2 0.1 0 ?0.1 ?0.2 0 500 1000 3000 09123-208 dnl (lsb) adc codes 3500 4000 4095 1500 2000 2500 figure 9. typical dnl error, temperature 25c, v ref = internal 2.5 v, single - ended mode adccp = adc0, adccn = adc0 , sampling rate = 345 khz worst case positive = 0.38 lsb, code 1567 worst case negative= ?0.24 lsb, code 4094 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.5 0.5 0.3 0.1 ?0.1 ?0.3 ?0.6 0 500 1000 3000 09123-209 inl (lsb) adc codes 3500 4000 4095 1500 2000 2500 figure 10 . typical inl error, temperature 25c, v ref = internal 2.5 v, single - ended mode adccp = adc0, adccn = adc0 , sampling rate = 345 khz worst case positive = 0.60 lsb, code 1890 worst case negative= 0.54 lsb, code 3485 0.3 0.4 0.2 0.1 0 ?0.1 ?0.2 09123-210 dnl (lsb) 0 500 1000 3000 adc codes 3500 4000 4095 1500 2000 2500 figure 11 . typical dnl error, temperature 25c, v ref = internal 2.5 v, single - ended mode adccp = dac1/adc13, adccn = adc0, sampling rate = 345 khz worst case positive = 0.40 lsb, code 607 worst case negative= 0.27 lsb, code 2486 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.5 0.5 0.3 0.1 ?0.1 ?0.3 ?0.6 09123-211 inl (lsb) 0 500 1000 3000 adc codes 3500 4000 4095 1500 2000 2500 figure 12 . typical inl error, temperature 25c, v ref = internal 2.5 v, single - ended mode adccp = dac1/adc13, a dccn = adc0, sampling rate = 345 khz worst case positive = 0.58 lsb, code 480 worst case negative= 0.54 lsb, code 3614 rev. d | page 24 o f 110
data sheet aduc7124/aduc7126 0.3 0.4 0.2 0.1 0 ?0.1 ?0.2 ?0.3 09123-212 dnl (lsb) 0 500 1000 3000 adc codes 3500 4000 4095 1500 2000 2500 figure 13 . typical dnl error, temperature 25c, v ref = internal 2.5 v, single - ended mode adccp = adc8, ad ccn = adc0, sampling rate = 345 khz worst - case positive = 0.42 lsb, code 3583 worst - case negative = ?0.32 lsb, code 3073 0.8 0.6 0 ?0.2 ?0.6 0.4 0.2 ?0.4 ?0.8 09123-213 inl (lsb) 0 500 1000 3000 adc codes 3500 4000 4095 1500 2000 2500 figure 14 . typical inl error, temperature 25c, v ref = internal 2.5 v, single - ended mode adccp = adc8, a dccn = adc0, sampling rate = 345 khz worst - case positive = 0.64 lsb, code 802 worst - case negative = 0.69 lsb, code 3485 0.3 0.4 0.2 0.1 0 ?0.1 ?0.2 09123-214 dnl (lsb) 0 500 1000 3000 adc codes 3500 4000 4095 1500 2000 2500 figure 15 . typical dnl error, temperature 25c, v ref = internal 2.5 v, single - ended mode adccp = dac3/ad c15, adccn = adc0, sampling rate = 345 khz worst - case positive = 0.41 lsb, code 2016 worst - case negative = 0.26 lsb, code 3841 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.5 0.5 0.3 0.1 ?0.1 ?0.3 ?0.6 09123-215 inl (lsb) ?0.6 0 500 1000 3000 adc codes 3500 4000 4095 1500 2000 2500 figure 16 . typical inl error, temperature 25c, v ref = internal 2.5 v, single - ended mode adccp = dac3/adc15, adccn = adc0, sampling rate = 345 khz worst - case positive = 0.55 lsb, code 738 worst - case negative = 0.68 lsb, code 3230 rev. d | page 25 of 110
aduc7124/aduc7126 data sheet 20 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 50 100 150 174.1 09123-216 sinad, thd, and phsn of adc (db) frequency (khz) snr: 69.85db thd: ?79.91db phsn: ?82.93db, 29.771khz figure 17 . sinad, thd, and phsn of adc, v ref = internal 2.5 v, single - ended mode adccp = ad c0 20 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 50 100 150 174.1 09123-217 sinad, thd, and phsn of adc (db) frequency (khz) snr: 67.10db thd: ?79.79db phsn: ?76.14db, 54.9738khz figure 18 . sinad, thd, and phsn of adc, v ref = internal 2.5 v, single - ended mode adccp = dac1/adc13, adccn = adc0 20 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 50 100 150 174.1 09123-218 sinad, thd, and phsn of adc (db) frequency (khz) snr: 67.44db thd: ?82.33db phsn: ?79.31db, 54.9738khz figure 19 . sinad, thd, and phsn of adc, v ref = internal 2.5 v, single - ended mode adccp = adc8, adccn = adc0 20 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 50 100 150 174.1 09123-219 sinad, thd, and phsn of adc (db) frequency (khz) snr: 65.97db thd: ?78.63db phsn: ?77.83db, 146.6038khz figure 20 . sinad, thd, and phsn of adc, v ref = internal 2.5 v, single - ended mode adccp = adc15/dac3, adccn = adc0 0.2 0.1 0 ?0.1 ?0.2 250 09123-220 dnl (lsb) adc codes 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4095 dac0 dac1 figure 21 . dac dnl error, dac0 max positive dnl: 0.18895 1, dac1 max positive dnl: 0.190343 dac0 max negative dnl: 0.120081, dac1 max negative dnl: 0.15697 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 250 09123-221 inl (lsb) adc codes 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4095 dac0 dac1 figure 22 . dac inl error, dac0 max positive inl: 1.84106, dac1 max positive inl: 1.75312 dac0 max negative inl: 0.887319, dac 1 max negative inl: 2.23708 rev. d | page 26 o f 110
data sheet aduc7124/aduc7126 terminology adc specifications integral nonlinearity (inl) the maximum deviation of any code from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero s cale, a point ? lsb below the first code transition, and full scale, a point ? lsb above the last code transition. differential nonlinearity (dnl) the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. off set error the deviation of the first code transition (0000000) to (0000001) from the ideal, that is, ? lsb. gain error the deviation of the last code transition from the ideal ain voltage (full scale ? 1.5 lsb) after the offset error has been adjusted out. signal to (noise + distortion) ratio the measured ratio of signal to (noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the rms sum of all non fundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent upon the number of quantization levels in the digitization process; the more levels there are, the smaller the quantization noise becomes. the theoretical signal to (noise + distortion) ratio for an ideal n - bit converter with a sine wave input is given by signal to ( noise + distortion ) = (6.02 n + 1.76) db thus, for a 12 - bit converter, this is 74 db. total harmonic distortion the ratio of the rms sum of the harmonics to the fundamental. dac specifications relative accuracy otherwise known as endpoint linearity, relative accuracy is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measur ed after adjusting for zero error and full - scale error. voltage output settling time the amount of time it takes the output to settle to within a 1 lsb level for a full - scale input change. rev. d | page 27 of 110
aduc7124/aduc7126 data sheet rev. d | page 28 of 110 overview of the arm7tdmi core the arm7? core is a 32-bit reduced instruction set computer (risc). it uses a single 32-bit bus for instruction and data. the length of the data can be eight bits, 16 bits, or 32 bits. the length of the instruction word is 32 bits. the arm7tdmi is an arm7 core with four additional features. ? t support for the thumb? (16-bit) instruction set. ? d support for debug. ? m support for long multiplications. ? i includes the embeddedice module to support embedded system debugging. thumb mode (t) an arm instruction is 32 bits long. the arm7tdmi processor supports a second instruction set that has been compressed into 16 bits, called the thumb instruction set. faster execution from 16-bit memory and greater code density can usually be achieved by using the thumb instruction set instead of the arm instruction set, which makes the arm7tdmi core particularly suitable for embedded applications. however, the thumb mode has two limitations: ? thumb code typically requires more instructions for the same job. as a result, arm code is usually best for maximizing the performance of time-critical code. ? the thumb instruction set does not include some of the instructions needed for exception handling, which automatically switches the core to arm code for exception handling. see the arm7tdmi user guide for details on the core architecture, the programming model, and both the arm and arm thumb instruction sets. long multiply (m) the arm7tdmi instruction set includes four extra instruc- tions that perform 32-bit by 32-bit multiplication with a 64-bit result and 32-bit by 32-bit multiplication-accumulation (mac) with a 64-bit result. these results are achieved in fewer cycles than required on a standard arm7 core. embeddedice (i) embeddedice provides integrated on-chip support for the core. the embeddedice module contains the breakpoint and watch- point registers that allow code to be halted for debugging purposes. these registers are controlled through the jtag test port. when a breakpoint or watchpoint is encountered, the processor halts and enters debug state. once in a debug state, the proces- sor registers can be inspected as well as the flash/ee, sram, and memory mapped registers. exceptions arm supports five types of exceptions and a privileged processing mode for each type. the five types of exceptions are ? normal interrupt or irq. this is provided to service general-purpose interrupt handling of internal and external events. ? fast interrupt or fiq. this is provided to service data transfers or communication channels with low latency. fiq has priority over irq. ? memory abort. ? attempted execution of an undefined instruction. ? software interrupt instruction (swi). this can be used to make a call to an operating system. typically, the programmer defines an interrupt as irq, but for higher priority interrupt, that is, faster response time, the programmer can define an interrupt as fiq. arm registers arm7tdmi has a total of 37 registers: 31 general-purpose registers and six status registers. each operating mode has dedicated banked registers. when writing user-level programs, 15 general-purpose, 32-bit registers (r0 to r14), the program counter (r15), and the current program status register (cpsr) are usable. the remaining registers are only used for system-level programming and exception handling. when an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. all excep- tion modes have replacement banked registers for the stack pointer (r13) and the link register (r14), as represented in figure 23. the fast interrupt mode has more registers (r8 to r12) for fast interrupt processing. this means that the interrupt processing can begin without the need to save or restore these registers, and therefore, save critical time in the interrupt handling process. 09123-007 usable in user mode system modes only spsr_und spsr_irq spsr_abt spsr_svc r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_fiq r14_fiq r13_und r14_und r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 (pc) r13_irq r14_irq r13_abt r14_abt r13_svc r14_svc spsr_fiq cpsr user mode fiq mode svc mode abort mode irq mode undefined mode figure 23. regist er organization
data sheet aduc7124/aduc7126 more information relative to the model of the programmer and the arm7tdmi core architecture can be found in the following materials from arm: ? ddi0029g, arm7tdmi technical reference manual ? ddi - 0100, arm architecture reference manual interrupt latency the worst - case latency for a fast interrupt request (fiq) consists of the following: ? the longest time the request can take to pass through the synchronizer ? the time for the longest instruction to complete (the longest instruction is an ldm) that loads all the registers including the pc ? the time for the data abort entry ? the time for the fiq entry at the end of this time, the arm7tdmi executes the instruction at 0x1c (fiq interrupt vector addres s). the maximum total time is 50 processor cycles, which is just under 1.2 s in a system using a continuous 41.78 mhz processor clock. the maximum interrupt request (irq) latency calculation is similar but must allow for the fact that fiq has higher prior ity and can delay entry into the irq handling routine for an arbitrary length of time. this time can be reduced to 42 cycles if the ldm command is not used. some compilers have an option to compile without using this command. another option is to run the p art in thumb mode where the time is reduced to 22 cycles. the minimum latency for fiq or irq interrupts is a total of five cycles, which consist of the shortest time the request can take through the synchronizer plus the time to enter the exception mode. n ote that the arm7tdmi always runs in arm (32 - bit) mode when in privileged modes, for example, when executing interrupt service routines. rev. d | page 29 of 110
aduc7124/aduc7126 data sheet memory organization the aduc7124 / aduc7126 incorporate three separate blocks of memory: 32 kb of sram and two 64 kb blocks of on - chip flash/ee memory. there are 126 kb of on - chip flash/ee memory available to the user, and the remaini ng 2 kb are reserved for the system kernel. these blocks are mapped as shown in figure 24. note that, by default, after a reset, the flash/ee memory is mirrored at address 0x00000000. it is possible to remap the s ram at address 0x00000000 by clearing bit 0 of the remap mmr. this remap function is described in more detail in the flash/ee memory chapter. reserved 0x00080000 flash/ee reserved 0x00047fff 0x00040000 sram 0xffff0000 0xffffffff mmrs 0x0001ffff 0x00000000 0x0009f800 reserved remappable memory space (flash/ee or sram) 09123-025 figure 24 . physical memory map memory access the arm7 core sees memory as a linear arra y of a 2 32 byte location where the different blocks of memory are mapped as outlined in figure 24. the aduc7124 / aduc7126 memory organization is configured in little endian format: the least significant byte is located in the lowest byte address and the most significant byte in the highest byte address. bit 31 byte 2 a 6 2 . . . byte 3 b 7 3 . . . byte 1 9 5 1 . . . byte 0 8 4 0 . . . bit 0 32 bits 0xffffffff 0x00000004 0x00000000 09123-026 figure 25 . little endian format flash/ee memory the 128 kb of flash/ee are or ganized as two banks of 32 k 16 bits. block 0 starts at address 0x90000 and finishses at address 0x9f700. in this block, 31 k 16 bits is user space and 1 k 16 bits is r eserved fo r the factory - configured boot page. the page size of this flash/ee memory is 512 bytes. block 1 starts at address 0x80000 and finishses at address 0x90000. in this block , all 64 kb are available as user space . the block is arranged in 32 k 16 b its. the 126 kb of flash/ee are available to the user as code and nonvolatile data memory. there is no distinction between data and program because arm code shares the same space. the real width of the flash/ee memory is 16 bits, meaning that, in arm mode (32 - bit instruction), two accesses to the flash/ee are necessary for each instruction fetch. therefore, it is recom - mended that thumb mode be used when executing from flash/ee memory for optimum access speed. the maximum access speed for the flash/ee memo ry is 41.78 mhz in thumb mode and 20.89 mhz in full arm mode (see the execution time from sram and flash/ee section). sram the 32 kb of sram are ava ilable to the user, organized as 8 k 32 bits, that is, 16 k wor ds. arm code can run directly from sram at 41.78 mhz , given that the sram array is configured as a 32 - bit wide memory array (see the execution time from sram and flash/ee section). memory mapped regist ers th e memory mapped register (mmr) space is mapped into the upper two pages of the memory array and accessed by indirect addressing through the arm7 banked registers. the mmr space provides an interface between the cpu and all on - chip peripherals. all register s except the core registers reside in the mmr area. all shaded locations shown in figure 26 are unoccupied or reserved locations and should not be accessed by user software. table 11 to table 29 show the full mmr memory map. the access time reading or writing a mmr depends on the advanced microcontroller bus architecture (amba) bus used to access the peripheral. the processor has two amba buses: the advanced high performance bus (ahb) used for system modules, and the advanced peripheral bus (apb) used for the lower performance peripheral. access to the ahb is one cycle, and access to the apb is two cycles. all peripherals on the aduc7124 / aduc7126 are on the apb except the flash/ee memory and the gpios. rev. d | page 30 o f 1 10
data sheet aduc7124/aduc7126 rev. d | page 31 of 110 09123-010 flash control interface 0 flash control interface 1 gpio pla pwm spi i2c1 i2c0 uart0 dac adc band gap reference power supply monitor pll and oscillator control watchdog timer wake-up timer general-purpose timer timer 0 remap and system control interrupt controller 0xffffffff 0xfffff800 0xfffff880 0xfffff400 0xfffff000 0xffff0f80 0xffff0b00 0xffff0a00 0xffff0900 0xffff0800 0xffff0700 uart1 0xffff0740 0xffff0600 0xffff0500 0xffff048c 0xffff0440 0xffff0404 0xffff0360 0xffff0340 0xffff0320 0xffff0300 0xffff0220 0xffff0000 external memory figure 26. memory mapped registers
aduc7124/aduc7126 data sheet table 11 . irq base address = 0xffff0000 address name byte access type 0xffff0000 irqsta 4 r 0xffff0004 irqsig 4 r 0xffff0008 irqen 4 r/w 0xffff000c irqclr 4 w 0xffff0010 swicfg 4 w 0xffff0014 irqbase 4 r/w 0xffff001c irqvec 4 r 0xffff0020 irqp0 4 r/w 0xffff0024 irqp1 4 r/w 0xffff0028 irqp2 4 r/w 0xffff002c irqp3 4 r/w 0xffff0030 irqconn 1 r/w 0xffff0034 irqcone 4 r/w 0xffff0038 irqclre 1 w 0xffff003c irqstan 1 r/w 0xffff0100 fiqsta 4 r 0xfff f0104 fiqsig 4 r 0xffff0108 fiqen 4 r/w 0xffff010c fiqclr 4 w 0xffff011c fiqvec 4 r 0xffff013c fiqstan 1 r/w table 12 . system control base address = 0xffff0200 address name byte access type 0xffff0220 remap 1 r/w 0xffff0230 rststa 1 r 0xffff0234 rstclr 1 w 0xffff0248 rstkey0 1 w 0xffff024c rstcfg 1 r/w 0xffff0250 rstkey1 1 w table 13 . timer base address = 0xffff0300 address name byte access type 0x ffff 0300 t0ld 2 r/w 0x ffff 0304 t0val 2 r 0x f fff 0308 t0con 2 r/w 0x ffff 030c t0clri 1 w 0x ffff 0320 t1ld 4 r/w 0x ffff 0324 t1val 4 r 0x ffff 0328 t1con 2 r/w 0x ffff 032c t1clri 1 w 0x ffff 0330 t1cap 4 r 0x ffff 0340 t2ld 4 r/w 0x ffff 0344 t2val 4 r 0x ffff 0348 t2con 2 r/w 0x ffff 034c t2clri 1 w 0x ffff 0360 t3ld 2 r/w 0x ffff 0364 t3val 2 r 0x ffff 0368 t3con 2 r/w 0x ffff 036c t3clri 1 w rev. d | page 32 o f 110
data sheet aduc7124/aduc7126 table 14 . pll/psm base address = 0xffff0400 address name byte access type 0xffff0404 powkey1 2 w 0xffff0408 powcon0 1 r/w 0xffff040c powkey 2 2 w 0xffff0410 pllkey1 4 w 0xffff0414 pllcon 1 r/w 0xffff0418 pllkey2 4 w 0xffff0434 powkey3 2 w 0xffff0438 powcon1 2 r/w 0xffff043c powkey4 2 w table 15 . psm base address = 0xffff0440 address name byte access type 0xff ff0440 psmcon 2 r/w 0x ffff 0444 cmpcon 2 r/w table 16 . reference base address = 0xffff0480 address name byte access type 0xffff048c refcon 1 r/w table 17 . adc base address = 0xffff0500 address name b yte access type 0x ffff 0500 adccon 2 r/w 0x ffff 0504 adccp 1 r/w 0x ffff 0508 adccn 1 r/w 0x ffff 050c adcsta 1 r 0x ffff 0510 adcdat 4 r 0x ffff 0514 adcrst 1 r/w 0x ffff 0530 adcgn 2 r/w 0x ffff 0534 adcof 2 r/w 0x ffff 0544 tscon 1 r/w 0x ffff 0548 tempref 2 r/ w table 18. dac address base = 0xffff0600 address name byte access type 0x ffff 0600 dac0con 1 r/w 0x ffff 0604 dac0dat 4 r/w 0x ffff 0608 dac1con 1 r/w 0x ffff 060c dac1dat 4 r/w 0x ffff 0610 dac2con 1 r/w 0x ffff 0614 dac2dat 4 r/w 0x ffff 0618 dac3con 1 r/w 0x ffff 061c dac3dat 4 r/w 0xffff0650 dacbkey1 2 w 0xffff0654 dacbcfg 1 r/w 0xffff0658 dacbkey2 2 w rev. d | page 33 of 110
aduc7124/aduc7126 data sheet table 19 . uart0 base address = 0xffff0 7 00 address name byte access type cycle 0x ffff 0700 com0tx 1 r /w 2 0x ffff 0700 com0rx 1 r 2 0x ffff 0700 com0div0 1 r/w 2 0x ffff 0704 com0ien0 1 r/w 2 0x ffff 0704 com0div1 1 r/w 2 0x ffff 0708 com0iid0 1 r 2 0x ffff 0708 com0fcr 1 r/w 2 0x ffff 070c com0con0 1 r/w 2 0x ffff 0710 com0con1 1 r/w 2 0x ffff 0714 com0sta0 2 r 2 0x ffff 0718 com0sta1 2 r 2 0xffff072c com0div2 2 r/w 2 table 20 . uart1 base address = 0xffff0 7 40 address name byte access type cycle 0x ffff 0740 com1tx 1 r/w 2 0x ffff 0740 com1rx 1 r 2 0x ffff 0740 com1div0 1 r/w 2 0x ffff 0744 com1ien0 1 r/w 2 0x ffff 0744 com1div1 1 r/w 2 0x ffff 0748 com1iid0 1 r 2 0x ffff 0748 com1fcr 1 r/w 0x ffff 074c com1con0 1 r/w 2 0x ffff 0750 com1con1 1 r/w 2 0x ffff 0754 com1sta0 2 r 2 0x ffff 0758 com1sta1 2 r 2 0xffff076c com1div2 2 r/w 2 table 21 . i2c0 base address = 0xffff0800 address name byte access type cycle 0xffff0800 i2c0mcon 2 r/w 2 0xffff0804 i2c0msta 2 r 2 0xffff0808 i2c0mrx 1 r 2 0xffff080c i2c0mtx 2 r/w 2 0xffff0810 i2c0mcnt0 2 r/w 2 0xffff0814 i2c0mcnt1 1 r 2 0xffff0818 i2c0adr0 1 r/w 2 0xffff081c i2c0adr1 1 r/w 2 0xffff0824 i2c0div 2 r/w 2 0xffff0828 i2c0scon 2 r/w 2 0xffff082c i2c0ssta 2 r 2 0xffff0830 i2c0srx 1 r 2 0xffff0834 i2c0stx 1 w 2 0xffff0838 i2c0alt 1 r/w 2 0xffff083c i2c0id0 1 r/w 2 0xf fff0840 i2c0id1 1 r/w 2 0xffff0844 i2c0id2 1 r/w 2 0xffff0848 i2c0id3 1 r/w 2 0xffff084c i2c0fsta 1 r/w 2 rev. d | page 34 o f 110
data sheet aduc7124/aduc7126 table 22 . i2c1 base address = 0xffff0900 address name byte access type cycle 0xffff0900 i2c1mcon 2 r/w 2 0xffff0904 i 2c1msta 2 r 2 0xffff0908 i2c1mrx 1 r 2 0xffff090c i2c1mtx 2 r/w 2 0xffff0910 i2c1mcnt0 2 r/w 2 0xffff0914 i2c1mcnt1 1 r 2 0xffff0918 i2c1adr0 1 r/w 2 0xffff091c i2c1adr1 1 r/w 2 0xffff0924 i2c1div 2 r/w 2 0xffff0928 i2c1scon 2 r/w 2 0xffff092c i2c 1ssta 2 r 2 0xffff0930 i2c1srx 1 r 2 0xffff0934 i2c1stx 1 w 2 0xffff0938 i2c1alt 1 r/w 2 0xffff093c i2c1id0 1 r/w 2 0xffff0940 i2c1id1 1 r/w 2 0xffff0944 i2c1id2 1 r/w 2 0xffff0948 i2c1id3 1 r/w 2 0xffff094c i2c1fsta 1 r/w 2 table 23 . spi base address = 0xffff0a00 address name byte access type cycle 0xffff0a00 spista 2 r 2 0xffff0a04 spirx 1 r 2 0xffff0a08 spitx 1 w 2 0xffff0a0c spidiv 1 r/w 2 0xffff0a10 spicon 2 r/w 2 table 24 . pla base add ress = 0xffff0b00 address name byte access type cycle 0xffff0b00 plaelm0 2 r/w 2 0xffff0b04 plaelm1 2 r/w 2 0xffff0b08 plaelm2 2 r/w 2 0xffff0b0c plaelm3 2 r/w 2 0xffff0b10 plaelm4 2 r/w 2 0xffff0b14 plaelm5 2 r/w 2 0xffff0b18 plaelm6 2 r/w 2 0xfff f0b1c plaelm7 2 r/w 2 0xffff0b20 plaelm8 2 r/w 2 0xffff0b24 plaelm9 2 r/w 2 0xffff0b28 plaelm10 2 r/w 2 0xffff0b2c plaelm11 2 r/w 2 0xffff0b30 plaelm12 2 r/w 2 0xffff0b34 plaelm13 2 r/w 2 0xffff0b38 plaelm14 2 r/w 2 0xffff0b3c plaelm15 2 r/w 2 0xf fff0b40 placlk 1 r/w 2 0xffff0b44 plairq 2 r/w 2 0xffff0b48 plaadc 4 r/w 2 0xffff0b4c pladin 4 r/w 2 0xffff0b50 pladout 4 r 2 0xffff0b54 plalck 1 w 2 rev. d | page 35 of 110
aduc7124/aduc7126 data sheet table 25 . pwm base address = 0xffff0f80 address name byte access type cycl e 0xffff0f80 pwmcon0 2 r/w 2 0xffff0f84 pwm0com0 2 r/w 2 0xffff0f88 pwm0com1 2 r/w 2 0xffff0f8c pwm0com2 2 r/w 2 0xffff0f90 pwm0len 2 r/w 2 0xffff0f94 pwm1com0 2 r/w 2 0xffff0f98 pwm1com1 2 r/w 2 0xffff0f9c pwm1com2 2 r/w 2 0xffff0fa0 pwm1len 2 r/ w 2 0xffff0fa4 pwm2com0 2 r/w 2 0xffff0fa8 pwm2com1 2 r/w 2 0xffff0fac pwm2com2 2 r/w 2 0xffff0fb0 pwm2len 2 r/w 2 0xffff0fb4 pwmcon1 2 r/w 2 0xffff0fb8 pwmclri 2 w 2 table 26. external memory base address = 0xfffff000 addre ss name byte access type cycle 0xf fff f000 xmcfg 1 r/w 2 0xf fff f010 xm0con 1 r/w 2 0xf fff f014 xm1con 1 r/w 2 0xf fff f018 xm2con 1 r/w 2 0xf fff f01c xm3con 1 r/w 2 0xf fff f020 xm0par 2 r/w 2 0xf fff f024 xm1par 2 r/w 2 0xf fff f028 xm2par 2 r/w 2 0xf fff f02 c xm3par 2 r/w 2 rev. d | page 36 o f 110
data sheet aduc7124/aduc7126 table 27 . gpio base address = 0xffff0400 address name byte access type cycle 0xf ffff 400 gp0con 4 r/w 1 0xf ffff 404 gp1con 4 r/w 1 0xf ffff 408 gp2con 4 r/w 1 0xf ffff 40c gp3con 4 r/w 1 0xf ffff 410 gp4con 4 r/w 1 0xf ffff 420 gp0dat 4 r/w 1 0xf ffff 424 gp0set 1 w 1 0xf ffff 428 gp0clr 1 w 1 0xf ffff 42c gp0par 4 r/w 1 0xf ffff 430 gp1dat 4 r/w 1 0xf ffff 434 gp1set 1 w 1 0xf ffff 438 gp1clr 1 w 1 0xf ffff 43c gp1par 4 r/w 1 0xf ffff 440 gp2dat 4 r/w 1 0xf ffff 444 gp2set 1 w 1 0xf ffff 448 gp2clr 1 w 1 0xf ffff 44c gp2par 4 r/w 1 0xf ffff 450 gp3dat 4 r/w 1 0xf ffff 454 gp3set 1 w 1 0xf ffff 458 gp3clr 1 w 1 0xf ffff 45c gp3par 4 r/w 1 0xf ffff 460 gp4dat 4 r/w 1 0xf ffff 464 gp4set 1 w 1 0xf ffff 468 gp4clr 1 w 1 0xf ffff 46c gp4par 4 r/w 1 table 28 . flash/ee block 0 base address = 0xfffff800 address name byte access type cycle 0xfffff800 fee0sta 1 r 1 0xfffff804 fee0mod 1 r/w 1 0xfffff808 fee0con 1 r/w 1 0xfffff80c fee0dat 2 r/w 1 0xfffff810 fee0adr 2 r/w 1 0xfffff818 fee0sgn 3 r 1 0xfffff81c fee0pro 4 r/w 1 0xfffff820 fee0hid 4 r/w 1 table 29 . flash/ee block 1 base address = 0xfffff880 address name byte access type cycle 0xfffff880 fee1sta 1 r 1 0xfffff884 fee1mod 1 r/ w 1 0xfffff888 fee1con 1 r/w 1 0xfffff88c fee1dat 2 r/w 1 0xfffff890 fee1adr 2 r/w 1 0xfffff898 fee1sgn 3 r 1 0xfffff89c fee1pro 4 r/w 1 0xfffff8a0 fee1hid 4 r/w 1 rev. d | page 37 of 110
aduc7124/aduc7126 data sheet rev. d | page 38 of 110 adc circuit overview the analog-to-digital converter is a fast, multichannel, 12-bit adc. it can operate from 2.7 v to 3.6 v supplies and is capable of providing a throughput of up to 1 msps when the clock source is 41.78 mhz. this block provides the user with a multichannel multiplexer, a differential track-and-hold, an on-chip reference, and an adc. the adc consists of a 12-bit successive approximation con- verter based around two capacitor dacs. depending on the input signal configuration, the adc can operate in one of three different modes. ? fully differential mode, for small and balanced signals ? single-ended mode, for any single-ended signals ? pseudo differential mode, for any single-ended signals, taking advantage of the common-mode rejection offered by the pseudo differential input the converter accepts an analog input range of 0 v to v ref when operating in single-ended or pseudo differential mode. in fully differential mode, the input signal must be balanced around a common-mode voltage (v cm ) in the 0 v to av dd range with a maximum amplitude of 2 v ref (see figure 27). 09123-011 av dd v cm v cm v cm 0 2v ref 2v ref 2v ref figure 27. examples of balanced signals in fully differential mode a high precision, low drift, factory calibrated, 2.5 v reference is provided on chip. an external reference can also be connected as described in the band gap reference section. single or continuous conversion modes can be initiated in the software. an external conv start pin, an output generated from the on-chip pla, or a timer0 or timer1 overflow can also be used to generate a repetitive trigger for adc conversions. a voltage output from an on-chip band gap reference propor- tional to absolute temperature can also be routed through the front-end adc multiplexer, effectively an additional adc channel input. this facilitates an internal temperature sensor channel that measures die temperature. transfer function pseudo differential and single-ended modes in pseudo differential or single-ended mode, the input range is 0 v to v ref . the output coding is straight binary in pseudo differential and single-ended modes with 1 lsb = full-scale /4096, or 2.5 v/4096 = 0.61 mv, or 610 v when v ref = 2.5 v the ideal code transitions occur midway between successive integer lsb values (that is, ? lsb, 3?2 lsb, 5?2 lsb, , fs ? 3/2 lsb). the ideal input/output transfer characteristic is shown in figure 28. 09123-012 output code voltage input 1111 1111 1111 1111 1111 1110 1111 1111 1101 1111 1111 1100 0000 0000 0011 1lsb0v +fs ? 1lsb 0000 0000 0010 0000 0000 0001 0000 0000 0000 1lsb = full- scale 4096 figure 28. adc transfer function in pseudo differential or single-ended mode fully differential mode the amplitude of the differential signal is the difference between the signals applied to the v in+ and v inC pins (that is, v in+ C v inC ). v in+ is selected by the adccp register, and v in? is selected by the adccn register. the maximum amplitude of the differential signal is, therefore, Cv ref to +v ref p-p (that is, 2 v ref ). this is regardless of the common mode (cm). the common mode is the average of the two signals, for example, (v in+ + v inC )/2, and is, therefore, the voltage that the two inputs are centered on. this results in the span of each input being cm v ref /2. this voltage must be set up externally, and its range varies with v ref (see the driving the analog inputs section). the output coding is twos complement in fully differential mode with 1 lsb = 2 v ref /4096, or 2 2.5 v/4096 = 1.22 mv when v ref = 2.5 v. the output result is 11 bits, but this is shifted by one to the right. this allows the result in adcdat to be declared as a signed integer when writing c code. the designed code transitions occur midway between successive integer lsb values (that is, ? lsb, 3?2 lsb, 5?2 lsb, , fs ? 3?2 lsb). the ideal input/output transfer characteristic is shown in figure 29. 09123-013 output code voltage input (v in + ? v in ?) 0 1111 1111 1110 0 1111 1111 1100 0 1111 1111 1010 0 0000 0000 0010 0 0000 0000 0000 1 1111 1111 1110 1 0000 0000 0100 1 0000 0000 0010 1 0000 0000 0000 ?v ref + 1lsb +v ref ? 1lsb 0lsb 1lsb = 2 v ref 4096 sign bit figure 29. adc transfer function in differential mode
data sheet aduc7124/aduc7126 rev. d | page 39 of 110 typical operation once configured via the adc control and channel selection registers, the adc converts the analog input and provides a 12-bit result in the adc data register. the top four bits are the sign bits. the 12-bit result is placed in bit 16 to bit 27 as shown in figure 30. again, it should be noted that in fully differential mode, the result is represented in twos complement format. in pseudo differential and single-ended modes, the result is represented in straight binary format. 09123-014 sign bits 12-bit adc result 31 27 16 15 0 figure 30. adc result format the same format is used in dacxdat, simplifying the software. current consumption the adc in standby mode, that is, powered up but not converting, typically consumes 640 a. the internal reference adds 140 a. during conversion, the extra current is 0.3 a multiplied by the sampling frequency (in khz). timing figure 31 gives details of the adc timing. the user controls the adc clock speed and the number of acquisition clocks in the adccon mmr. by default, the acquisition time is eight clocks, and the clock divider is two. the number of extra clocks (such as bit trial or write) is set to 19, which gives a sampling rate of 774 ksps. for conversion on temperature sensor, the adc acquisition time is automatically set to 16 clocks, and the adc clock divider is set to 32. when using multiple channels including the temperature sensor, the timing settings revert to the user-defined settings after reading the temperature sensor channel. 09123-015 adc clock acq bit trial data adcsta = 0 adcsta = 1 adc interrupt write conv start adc busy adcdat figure 31. adc timing mmrs interface the adc is controlled and configured via the eight mmrs. adccon register name: adccon address: 0xffff0500 default value: 0x0600 access: read/write adccon is an adc control register that allows the program- mer to enable the adc peripheral, select the mode of operation of the adc (either in single-ended mode, pseudo differential mode, or fully differential mode), and select the conversion type. this mmr is described in table 30. table 30. adccon mmr bit descriptions bit value description [15:14] reserved. 13 set by the user to enable edge trigger mode. cleared by the user to enable level trigger mode. [12:10] adc clock speed. 000 f adc /1. this divider is provided to obtain 1 msps adc with an external clock <41.78 mhz. 001 f adc /2 (default value). 010 f adc /4. 011 f adc /8. 100 f adc /16. 101 f adc /32. [9:8] adc acquisition time. 00 two clocks. 01 four clocks. 10 eight clocks (default value). 11 16 clocks. 7 enable start conversion. set by the user to start any type of conversion command. cleared by the user to disable a start conversion (clearing this bit does not stop the adc when continuously converting). 6 enable adc busy . set by the user to enable the adc busy pin. cleared by the user to disable the adc busy pin. 5 adc power control. set by the user to place the adc in normal mode (the adc must be powered up for at least 5 s before it converts correctly). cleared by the user to place the adc in power- down mode. [4:3] conversion mode. 00 single-ended mode. 01 differential mode. 10 pseudo differential mode. 11 reserved.
aduc7124/aduc7126 data sheet bi t value description [2:0] conversion type. 000 enable conv start pin as a conversion input. 001 enable timer1 as a conversion input. 010 enable timer0 as a conversion inpu t. 011 single software conversion. sets to 000 after conversion (note that bit 7 of adccon mmr should be cleared after starting a single software conversion to avoid further conversions triggered by the conv start pin). 100 continuous software conversio n. 101 pla conversion. other reserved. adccp register name: adccp address: 0xffff0504 default value: 0x00 access: read/write adccp is an adc positive channel selection register. this mmr is described in t able 31. table 31 . adccp 1 mmr bit designation bit value description [7:5] reserved. [4:0] positive channel selection bits. 00000 adc0. 00001 adc1. 00010 adc2. 00011 adc3. 00100 adc4. 00101 adc5. 00110 adc6. 001 11 adc7. 01000 adc8. 01001 adc9. 01010 adc10. 01011 adc11. 01100 dac0/adc12. 01101 dac1/adc13. 01110 dac2/adc14. 01111 dac3/adc15. 10000 temperature sensor. 10001 agnd (self - diagnostic feature). 10010 internal reference (self - diagnost ic feature). 10011 av dd /2. others reserved. 1 adc and dac channel availability depends on part model. see the ordering guide for details. rev. d | page 40 o f 110
data sheet aduc7124/aduc7126 adccn register name: adccn address: 0xffff0508 default value: 0x0 1 access: read/write adccn is an adc negative channel selection register. this mmr is described in table 32. table 32 . adccn mmr bit designation bit value description [7:5] reserved. [4:0] negative channel selection bits. 00000 adc0. 00001 adc1. 00010 adc2. 00011 adc3. 00100 adc4. 00101 adc5. 00110 adc6. 00111 adc7. 01000 adc8. 01001 adc9. 01010 adc10. 01011 adc11. 01100 dac0/adc12. 01101 dac1/adc13. 0111 0 dac2/adc14. 01111 dac3/adc15. 10000 reserved. 10001 agnd. 10010 reserved. 10011 reserved. others reserved. adcsta register name: adcsta address: 0xffff050c default value: 0x00 access: read only adcsta is an adc status register that indic ates when an adc conversion result is ready. the adcsta register contains only one bit, adcready (bit 0), representing the status of the adc. this bit is set at the end of an adc conversion, generating an adc interrupt. it is cleared automatically by readi ng the adcdat mmr. when the adc is performing a conversion, the status of the adc can be read externally via the adc busy pin. this pin is high during a conversion. when the conversion is finished, adc busy goes back low. this information is available on p0. 5 (see the general - purpose input/output section) if enabled in the adccon register. adcdat register name: adcdat address: 0xffff0510 default value: 0x00000000 access: read only adcdat is an adc data result register that holds the 12 - bit adc result, as shown in figure 30. adcrst register name: adcrst address: 0xffff0514 default value: 0x00 access: read/write adcrst resets the digital interface of the adc. writin g any value to this register resets all the adc registers to their default values . adcgn register name: adcgn address: 0xffff0530 default value: 0x0200 access: read/write adcgn is a 10 - bit gain calibration register. adcof register name: adcof address: 0xffff0534 default value: 0x0200 access: read/write adcof is a 10 - bit offset calibration register. converter operation the adc incorporates a successive approximation (sar) architecture involving a charge - sampled input stage. this architecture can oper ate in three different modes: differential, pseudo differential, and single - ended. differential mode the aduc7124 / adu c7126 each contains a successive approx - imation adc based on two capacitive dacs. figure 32 and figure 33 show simplified schematics of the adc in acquisition and conv ersion phases, respectively. the adc comprises con - trol logic, a sar, and two capacitive dacs. in figure 32 (the acquisition phase), sw3 is closed and sw1 and sw2 are in rev. d | page 41 of 110
aduc7124/aduc7126 data sheet rev. d | page 42 of 110 position a. the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input. 09123 -017 capacitive dac capacitive dac control logic comparator sw3 sw1 a a b b sw2 c s c s v ref ain0 ain11 mux channel+ channel? figure 32. adc acquisition phase when the adc starts a conversion, as shown in figure 33, sw3 opens, and then sw1 and sw2 move to position b. this causes the comparator to become unbalanced. both inputs are discon- nected once the conversion begins. the control logic and the charge redistribution dacs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code. the output impedances of the sources driving the v in+ and v inC pins must be matched; otherwise, the two inputs have different settling times, resulting in errors. 09123 -018 capacitive dac capacitive dac control logic comparator sw3 sw1 a a b b sw2 c s c s v ref ain0 ain11 mux channel+ channel? figure 33. adc conversion phase pseudo differential mode in pseudo differential mode, channel? is linked to the adcneg pin of the aduc7124 / aduc7126 . in figure 34, adcneg is represented as v in? . sw2 switches between a (channel?) and b (v ref ). the adcneg pin must be connected to ground or to a low voltage. the input signal on v in+ can then vary from v in? to v ref + v in? . note that v in? must be chosen so that v ref + v in? do not exceed av dd . 09123 -019 capacitive dac capacitive dac control logic comparator sw3 sw1 a a b b sw2 c s c s v ref ain0 ain11 v in? mux channel+ channel? figure 34. adc in pseudo differential mode single-ended mode in single-ended mode, sw2 is always connected internally to ground. the v in? pin can be floating. the input signal range on v in+ is 0 v to v ref . 09123 -020 capacitive dac capacitive dac control logic comparator sw3 sw1 a b c s c s ain0 ain11 mux channel+ channel? figure 35. adc in single-ended mode analog input structure figure 36 shows the equivalent circ uit of the analog input structure of the adc. the four diodes provide esd protection for the analog inputs. care must be taken to ensure that the analog input signals never exceed the supply ra ils by more than 300 mv; this can cause these diodes to beco me forward-biased and start conducting into the substrate. th ese diodes can conduct up to 10 ma without causing irrevers ible damage to the part. the c1 capacitors in figure 36 are typically 4 pf and can be primarily attributed to pin capacitance. the resistors are lumped components made up of the on resistance of the switches. the value of these resistors is typically about 100 . the c2 capacitors are the sampling capacitors of the adc and typically have a capacitance of 16 pf. a v dd c1 d d r1 c2 av dd c1 d d r1 c2 09123-021 figure 36. equivalent analog input circuit conversion phase: switches open, track phase: switches closed
data sheet aduc7124/aduc7126 for ac applications, removing high frequency components from the analog input signal is recommended by using an rc low - pass filter on the relevant analog input pins. in applications where harmonic distortion and signal - to - noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances significantly affect the ac performance of the adc. this can necessitate the use of an in put buffer amplifier. the choice of the op amp is a function of the particular application. figure 37 and figure 38 give an example of the adc front end. 09123-061 aduc7124/ aduc7126 adc0 10? 0.01f figure 37 . buffering single - ended/pseudo differential input 09123-062 aduc7124/ aduc7126 adc0 v ref adc1 figure 38 . buffering differential inputs when no amplifier is used to drive the analog input, the source impedance should be limited to values lower than 1 k?. the maximum source impedance depends on the amount of total harmonic distortion (thd) that can be tolerated. the thd increases as the source impedance increases and the performance degrades. driving the analog i nputs internal or external references c an be used for the adc. in differential mode of operation, there are restrictions on the common - mode input signal (v cm ), which is dependent upon the reference value and supply voltage used to ensure that the signal remains within the supply rails. table 33 gives some calculated v cm minimum and v cm maximum values. table 33. v cm ranges av dd v ref v cm minimum v cm maximum signal peak - to - peak 3.3 v 2.5 v 1.25 v 2.05 v 2.5 v 2.048 v 1.024 v 2 .276 v 2.048 v 1.25 v 0.75 v 2.55 v 1.25 v 3.0 v 2.5 v 1.25 v 1.75 v 2.5 v 2.048 v 1.024 v 1.976 v 2.048 v 1.25 v 0.75 v 2.25 v 1.25 v rev. d | page 43 of 110
aduc7124/aduc7126 data sheet calibration by default, the factory - set values written to the adc offset (adcof) and gain coefficient register s (adcgn) yield opti - mum performance in terms of end - point errors and linearity for standalone operation of the part (see the specifications section). if system calibration is required, it is possible to mod ify the default offset and gain coefficients to improve end - point errors, but note that any modification to the factory - set adcof and adcgn values can degrade adc linearity performance. for system offset error correction, the adc channel input stage must b e tied to agnd. a continuous software adc conversion loop must be implemented by modifying the value in adcof until the adc result (adcdat) reads code 0 to code 1. if the adcdat value is greater than 1, adcof should be decremented until adcdat reads code 0 to code 1. offset error correction is done digitally and has a resolution of 0.25 lsb and a range of 3.125% of v ref . for system gain error correction, the adc channel input stage must be tied to v ref . a continuous software adc conversion loop must be imp lemented to modify the value in adcgn until the adc result (adcdat) reads code 4094 to code 4095. if the adcdat value is less than 4094, adcgn should be incremented until adcdat reads code 4094 to code 4095. similar to the offset calibration, the gain cali bration resolution is 0.25 lsb with a range of 3% of v ref . temperature sensor the aduc7124 / aduc7126 provide voltage outputs from an on - chip band gap reference that is proportional to absolute temperature. this voltage output can also be routed through the front - end adc multiplexer (effectively, an additional adc channel input), facilitating an internal temperature sens or channel, measuring die temperature. an adc temperature sensor conversion differs from a standard adc voltage. the adc performance specifications do not apply to the temperature sensor. chopping of the internal amplifier must be enabled using the tscon register. to enable this mode, the user must set bit 0 of tscon. the user must also take two consecutive adc readings and average them in this mode. the adccon register must be configured to 0x37a3. to calculate die temperature, use the following formula: t C t ref = ( v adc C v tref ) k where: t is the temperature result. t ref = 25c. for the aduc7124 , v tref = 1.415 v and for the aduc7126 , v tref = 1.392 v, which corresponds to t ref = 25c, as described in table 1 . v adc is the average adc result from two consecutive conversions. k is the gain of the adc in temperature sensor mod e as determined by characterization data. k = 0.2555c/mv for aduc7124 . k = 0.2212c/mv for aduc7126 . this correspo nds to the 1/voltage temperature coefficient specification from table 1. using the default values from table 1 and without any calibration, this equation becomes t ? 25c = ( v adc ? 1415) 0.2555 for aduc7124 t ? 25c = ( v adc ?1392) 0.2212 for aduc7126 where v adc is in mv. for better accuracy, the user should perform a single point calibration at a controlled temperature value. for the calculation with no calibration, use 25c and 1415 m v for the aduc7124 an d 1392mv for the aduc7126 . the idea of a single point calibration is to use other known (t ref , v tref ) values to replace the common t = 25c and 1415 m v for the aduc7124 and 1392 mv for the aduc7126 for every part. for some users, it is not possible to obtain such a known pair. for such cases, the aduc7124 / aduc7126 comes with a single point calibration value loaded in the tempref register. for more details on thi s register, see table 35 . during production testing of the aduc7124 / aduc7 126 , the tempref register is loaded with an offset adjustment factor. each part has a different value in the tempref register. using this single point calibration, the same formula is still used. t C t ref = ( v adc C v tref ) k where: t ref = 25c but is not guaranteed. v tref can be calculated using the tempref register. tscon register name: tscon address: 0xffff0544 default value: 0x00 access: read/write table 34 . tscon mmr bit descriptions bit description [7:1] reserved. 0 temp erature sensor chop enable bit. this bit must be set. this bit is set to 1 to enable chopping of the internal amplifier to the adc. this bit is cleared to disable chopping. this results in incorrect temperature sensor readings. this bit is cleared by default. rev. d | page 44 o f 110
data sheet aduc7124/aduc7126 tempref register name: tempref address: 0xffff0548 default value: 0xxxxx access: read/write table 35 . tempref mmr bit descriptions bit description [15:9] reserved. 8 temperature reference voltage sign bit. [7:0] t emperature sensor offset calibration voltage. to calculate the v temp from the tempref register, perform the following calculation: if tempref sign is negative, c tref = 2292 ? tempref[7:0] where tempref[8] = 1 or if tempref sign is positive, c tref = tempref[7:0] + 2292 where tempref[8] = 0. finally, v tref = (( c tref v ref )/4096) 1000 insert v tref into t ? t ref = ( v adc ? v tref ) k note that the adc code value 229 2 is a default value when using the tempref register. it is not an exact value and must only be used with the tempref register. band gap reference each aduc7124 / aduc7126 provides on - chip band gap references of 2.5 v, which can be used for the adc and dac. this internal reference also appears on the v ref pin. when using the internal reference, a 0.47 f capacitor must be connected from the external v ref pin to agnd to ensure stability and fast response during adc conversions. this reference can also be connected to an external pin (v ref ) and used as a reference for other circuits in the system. an external buffer is re quired because of the low drive capability of the vref output (<5 a). a programmable option also allows an external reference input on the v ref pin. note that it is not possible to disable the internal reference. therefore, the external reference source m ust be capable of overdriving the internal reference source. refcon register name: refcon address: 0xffff048c default value: 0x00 access: read/write the band gap reference interface consists of an 8 - bit mmr refcon, described in table 36 . table 36 . refcon mmr bit descriptions bit description [7:2] reserved. 1 internal reference power - down bit. set this bit to 1 to power down the internal reference source. this bit should be set when co nnecting an external reference source. clear this bit to enable the internal reference. this bit is cleared by default. 0 internal reference output enable. set by the user to connect the internal 2.5 v reference to the v ref pin. the reference can be used for an external component but must be buffered. cleared by the user to disconnect the reference from the v ref pin. to connect an external reference source to the aduc7124 / aduc7126 , configure refcon = 0x00. adc and the dacs can be configured to use same or a different reference resource (see table 66). rev. d | page 45 of 110
aduc7124/aduc7126 data sheet nonvolatile flash/ee memory the aduc7124 / aduc7126 incorporate flash/ee memory technology on - chip to provide the user with nonvolatile, in - circuit reprogrammable memory space. like eeprom, flash memory can be programmed in - system at a byte level, although it must first be erased. the erase is performed in page blocks. as a result, flash memory is often and more correctly referred to as fl ash/ee memory. overall, flash/ee memory represents a step closer to the ideal memory device that includes nonvolatility, in - circuit programmability, high density, and low cost. incorporated in the aduc7124 / aduc7126 , flash/ee memory technology allows the user to update program code space in - circuit, without the need to replace one - time programmable (otp) devices at remo te operating nodes. flash/ee memory the aduc7124 / aduc7126 con tain two 64 kb arrays of flash/ee memory. in flash b loc k 0 , the lower 62 kb is available to the user, and the upper 2 kb of this f lash/ee program memory array contain permanently embedded firmware, allowing in - circuit serial download. the 2 kb of embedded firmware also contain a power - on configuration routine that downloads factory cali - brated coefficients to the various calibrated peripherals (band gap references and so on). this 2 kb embedded firmware is hidden from user code. it is not possible for the user to read, write, or erase this page. in flash b lock 1 , all 64 kb of flash/ee memory are available to the user . the 126 kb of flash/ee memory can be programmed in - circuit, using the serial download mode or the jtag mode provided. flash/ee memory reliability the flash/ee memory arrays on the parts are fully q ualified for two key flash/ee memory characteristics: flash/ee memory cycling endurance and flash/ee memory data retention. endurance quantifies the ability of the flash/ee memory to be cycled through many program, read, and erase cycles. a single enduranc e cycle is composed of four independent, sequential events, defined as 1. initial page erase sequence. 2. read/verify sequence (single flash/ee). 3. byte program sequence memory. 4. second read/verify sequence (endurance cycle). in reliability qualification, every hal f word (16 - bit wide) location of the three pages (top, middle, and bottom) in the flash/ee memory is cycled 10,000 times from 0x0000 to 0xffff. as indicated in table 1 , the flash/ee memory endurance qualificati on is carried out in accordance with jedec retention lifetime specification a117 over the industrial temperature range of ?40 to +125c. the results allow the specification of a minimum endurance figure over a supply temperature of 10,000 cycles. retentio n quantifies the ability of the flash/ee memory to retain its programmed data over time. again, the parts are qualified in accordance with the formal jedec retention lifetime specification (a117) at a specific junction temperature (t j = 85c). as part of t his qualification procedure, the flash/ee memory is cycled to its specified endurance limit (see the flash/ee memory section) before data retention is character - ized. this means that the flash/ee memory is guaran teed to retain its data for its fully specified retention lifetime every time the flash/ee memory is reprogrammed. in addition, note that retention lifetime, based on the activation energy of 0.6 ev, derates with t j as shown in figure 39. 150 300 450 600 30 40 55 70 85 100 125 135 150 retention (years) 0 09123-085 junction temperature (c) figure 39 . flash/ee memory data retention programming the 126 kb of flash/ee memory can be programmed in - circuit, using the serial download mode or the provided jtag mode. serial downloading (in - circuit programming) the aduc7124 / aduc7126 facilitate code download via the standard uart serial port. it is only available on uart0 (p 1.0 and p1.1). the parts enter serial download mode after a reset or power cycle if the bm pin is pulled low through an external 1 k? resistor. when in serial download mode, the user can download code to the full 126 kb of flash/ee memory while the device is in - circuit in its target application hardware. an executable pc serial download is provided as part of the devel opment system for serial downloading via the uart. the an - 724 application note describes the uart download protocol. downloading (in - circuit programming) via i 2 c the aduc7126bstz126i and ad uc7126bstz126irl models facilitate code download via the the i 2 c port. the model s enter download mode after a reset or power cycle if the bm pin is pulled low through an external 1 k? resistor and flash address 0x80014 = 0xffffffff. once in download mode, the user can download code to the full 126 kb of flash/ee memory while the devic e is in - circuit in its target application hardware. an executable pc i 2 c download is provided as part of the development system rev. d | page 46 o f 110
data sheet aduc7124/aduc7126 for serial downloading via the i 2 c. a usb - to - i 2 c download dongle can be purchased from analog devices, inc. this board connects to the usb port of a pc and to the i 2 c port of the aduc7126 . the part number is usb - i2c/lin - conv - z. the an - 806 applicati on note describes the protocol for serial downloading via the i 2 c in more detail. jtag access the jtag protocol uses the on - chip jtag interface to facilitate code download and debug. to access the part via the jtag interface, the p0.0/bm pin must be set high. when debugging, user code should not write to the p0.1, p0.2, and p0.3 pins. if user code toggles any of these pins, jtag debug pods are not able to connect to the aduc7124 / aduc7126 . if this happens, mass erase the part using the uart/i 2 c downloader. flash/ee memory secu rity the 126 kb of flash/ee memory available to the user can be read and write protected. bit 31 of the fee0pro/fee0hid mmr protects the 62 kb of block 0 from being read through jtag and in uart programming mode. the other 31 bits of this register protect writing to the flash/ee memory; each bit protects four pages, that is, 2 kb. write protection is activated for all access types . fee1pro and fee1hid, similarly, protect flash block 1 . bit 31 of the fee1pro/fee1hid mmr protects the 64 kb of block 1 from being read through jtag. bit 30 protects writing to the top 8 pages of block 1. the other 30 bits of this register protect writing to the flash/ee memory; each bit protects four pages, that is, 2 kb three levels of protection ? protection can be set and removed by writing directly into feexhid mmr. this protection does not remain after reset. ? protection can be set by writing into feexpro mmr. it takes effect only after a save protection command (0x0c) and a reset. the feexpro mmr is protected by a key to avoid direct access. the key is saved once and must be entered again to modify feexpro. a mass erase sets the key back to 0xffff but also erases all the user code. ? flash can be permanently protected by using the feexpro mmr and a particular key value of 0xdeaddead. entering the key again to modify the feexpro register is not allowed. sequence to write th e key 1. write the bit in feexpro corresponding to the page to be protected. 2. enable key protection by setting bit 6 of feexmod (bit 5 must equal 0). 3. write a 32 - bit key in feexadr and feexdat. 4. run the write key command 0x0c in feexcon; wait for the read to be successful by monitoring feexsta. 5. reset the part. to remove or modify the protection, the same sequence is used with a modified value of feexpro. if the key chosen is the value 0xdead, the memory protection cannot be removed. only a mass erase unprotects the part, but it also erases all user code. the sequence to write the key is illustrated in the following example (this protects writing page 4 to page 7 of the flash): feexpro=0xfffffffd; //protect page 4 to 7 feexmod=0x48; //write key enable feexadr=0x1234; //16 bit key value feexdat=0x5678; //16 bit key value feexcon= 0x0c; //write key command the same sequence should be followed to protect the part permanently with feexadr = 0xdead and feexdat = 0xdead . flash/ee control int erface table 37 . fee0sta register name address default value access fee0sta 0xfffff800 0x0000 r table 38 . fee0mod register name address default value access fee0mod 0xfffff804 0x80 r/w table 39 . fee0con regis ter name address default value access fee0con 0xfffff808 0x00 r/w table 40 . fee0dat register name address default value access fee0dat 0xfffff80c 0xxxxx r/w fee0dat is a 16 - bit data register . table 41. fee0adr register name address default value access fee0adr 0xfffff810 0x0000 r/w fee0adr is a 16 - bit address register . table 42 . fee0sgn register name address default value access fee0sgn 0xfffff818 0xffffff r fee0sgn is a 24- bit code signature. table 43 . fee0pro register name address default value access fee0pro 0xfffff81c 0x00000000 r/w fee0pro provides protection following subsequent reset mmr. it requires a software key (see table 56). table 44 . fee0hid register name address default value access fee0hid 0xfffff820 0xffffffff r/w fee0hid provides immediate protection mmr. it does not require any software keys (see table 56). rev. d | page 47 of 110
aduc7124/aduc7126 data sheet table 45 . fee1sta register name address default value access fee1sta 0xfffff880 0x0000 r table 46 . fee1mod register name address default value access fee1mod 0xfffff88 4 0x80 r/w table 47 . fee1con register name address default value access fee1con 0xfffff888 0x00 r/w table 48 . fee1dat register name address default value access fee1dat 0xfffff88c 0xxxxx r/w fee1dat is a 16 - bit data register . table 49 . fee1adr register name address default value access fee1adr 0xfffff890 0x0000 r/w fee1adr is a 16 - bit address register . table 50 . fee1sgn register name address default v alue access fee1sgn 0xfffff898 0xffffff r fee1sgn is a 24- bit code signature. table 51 . fee1pro register name address default value access fee1pro 0xfffff89c 0x00000000 r/w fee1pro provides protection following subsequent reset mmr. it requires a software key (see table 57). table 52 . fee1hid register name address default value access fee1hid 0xfffff8a0 0xffffffff r/w fee1hid provides immediate protection mmr. it does not require any software keys (see table 57). command sequence for executing a mass erase fee0dat = 0x3cff; fee0adr = 0xffc3; fee0mod = fee0mod|0x8; //erase key enable fee0con = 0x06; //mass erase command table 53 . feexsta mmr bit descriptions bit description [15:6] reserved. 5 reserved. 4 reserved. 3 flash/ee interrupt status bit. set automatically when an interrupt occurs, that is, when a command is complete and the flash/ ee interrupt enable bit in the feexmod register is set. cleared when reading the feexsta register. 2 flash/ee controller busy. set automatically when the controller is busy. cleared automatically when the controller is not busy. 1 command fail. set a utomatically when a command completes unsuccessfully. cleared automatically when reading the feexsta register. 0 command complete. set by microconverter when a command is complete. cleared automatically when reading the feexsta register. rev. d | page 48 o f 110
data sheet aduc7124/aduc7126 table 54 . feexmod mmr bit descriptions bit description [7:5] reserved. 4 flash/ee interrupt enable. set by the user to enable the flash/ee interrupt. the interrupt occurs when a command is complete. cleared by the user to disable the fla sh/ee interrupt. 3 erase/write command protection. set by the user to enable the erase and write commands. cleared to protect the flash/ee memory against the erase/write command. 2 reserved. should always be set to 0 by the user. [1:0] flash/ee wait s tates. both flash/ee blocks must have the same wait state value for any change to take effect. table 55 . command codes in feexcon code command description 0x00 1 null idle state. 0x01 1 single read load feexdat with the 16 - bit data indexed by feexadr. 0x02 1 single write write feexdat at the address pointed to by feexadr. this operation takes 50 s. 0x03 1 erase/write erase the page indexed by feexadr and write feexdat at the location pointed to by feexadr. this operation takes 20 ms. 0x04 1 single verify compare the contents of t he location pointed to by feexadr to the data in feexdat. the result of the comparison is returned in feexsta, bit 1. 0x05 1 single erase erase the page indexed by feexadr. 0x06 1 mass erase erase user space. the 2 kb of kernel are protected in block 0. this operation takes 2.48 sec. to prevent accidental execution, a command sequence is required to execute this instruction. 0x07 reserved reserved. 0x08 r eserved reserved. 0x09 reserved reserved. 0x0a reserved reserved. 0x0b signature gives a signature of the 64 kb of flash/ee in the 24 - bit feexsign mmr. this operation takes 32,778 clock cycles. 0x0c protect this command can be run only once. the value of feexpro is saved and can be removed only with a mass erase (0x06) or with the key. 0x0d reserved reserved. 0x0e reserved reserved. 0x0f ping no operation, interrupt generated. 1 the feexcon register always reads 0x07 immediately after execution of any of these commands. rev. d | page 49 of 110
aduc7124/aduc7126 data sheet table 56 . fee0pro and fee0hid mmr bit descri ptions bit description 31 read protection. cleared by the user to protect block 0. set by the user to allow reading of block 0. [30:0] write protection for page 123 to page 0. each bit protects protects a group of 4 pages. cleared by the user to p rotect the pages when writing to flash. thus preventing an accidental write to specific pages in flash . set by the user to allow writing to the pages. table 57 . fee1pro and fee1hid mmr bit descriptions bit description 31 read protection. cleared by the user to protect block 1. set by the user to allow reading of block 1. 30 write protection for page 127 to page 120. cleared by the user to protect the pages when writing to flash. thus preventing an accidental write to s pecific pages in flash . set by the user to allow writing to the pages. [29:0] write protection for page 119 to page 116 and for page 0 to page 3. cleared by the user to protect the pages in writing. set by the user to allow writing to the pages. e xecution time from s ram and flash/ee this section describes sram and flash/ee access times during execution for applications where execution time is critical. execution from sram fetching instructions from sram takes one clock cycle because the access time of the sram is 2 ns, and a clock cycle is 24 ns minimum. however, if the instruction involves reading or writing data to memory, one extra cycle must be added if the data is in sram (or three cycles if the data is in flash/ee): one cycle to execute the in struction and two cycles to get the 32 - bit data from flash/ee. a control flow instruction (a branch instruction, for example) takes one cycle to fetch but also takes two cycles to fill the pipeline with the new instructions. execution from flash/ee because the flash/ee width is 16 bits and access time for 16 - bit words is 22 ns, execution from flash/ee cannot be done in one cycle (as can be done from sram when the cd bit = 0). also, some dead times are needed before accessing data for any value of the cd bi ts. in arm mode, where instructions are 32 bits, two cycles are needed to fetch any instruction when cd = 0. in thumb mode, where instructions are 16 bits, one cycle is needed to fetch any instruction. timing is identical in both modes when executing inst ructions that involve using the flash/ee for data memory. if the instruc - tion to be executed is a control flow instruction, an extra cycle is needed to decode the new address of the program counter, and then four cycles are needed to fill the pipeline. a d ata pro - cessing instruction involving only the core register does not require any extra clock cycles. however, if it involves data in flash/ee, an extra clock cycle is needed to decode the address of the data, and two cycles are needed to get the 32 - bit da ta from flash/ee. an extra cycle must also be added before fetching another instruction. data transfer instructions are more complex and are summarized in table 58 . table 58 . execution cyc les in arm/thumb mode instructions fetch cycles dead time data access dead time ld 1 2/1 1 2 1 ldh 2/1 1 1 1 ldm/push 2/1 n 2 2 n 2 n 1 str 1 2/1 1 2 20 ns 1 strh 2/1 1 20 ns 1 strm/pop 2/1 n 1 2 n 20 ns 1 n 1 1 the swap instruction combines an ld a nd str instruction with only one fetch, giving a total of eight cycles + 40 ns. 2 n is the number of data bytes to load or store in the multiple load/store instruction (1 < n 16). reset and remap the arm exception vectors are all situated at the bottom o f the memory array, from address 0x00000000 to address 0x00000020, as shown in figure 40. kernel interrupt service routines interrupt service routines arm exception vector addresses 0x00000020 0x00047fff 0x0009f800 0xffffffff flash/ee sram mirror space 0x00000000 0x00000000 0x00040000 0x00080000 09123-027 figure 40 . remap for exception execution by default, and after any reset, the flash/ee is mirr ored at the bottom of the memory array. the remap function allows the programmer to mirror the sram at the bottom of the memory array, which facilitates execution of exception routines from sram instead of from flash/ee. this means exceptions are executed twice as fast, being executed in 32 - bit arm mode with 32- bit wide sram instead of 16 - bit wide flash/ee memory. rev. d | page 50 o f 110
data sheet aduc7124/aduc7126 table 59 . remap mmr bit descriptions (address = 0xffff0220. default value = 0x00) bit name description 0 remap remap bit. set by the user to remap the sram to address 0x00000000. cleared automatically after reset to remap the flash/ee memory to address 0x00000000. remap operation when a reset occurs on the aduc7124 / aduc7126 , execution automatically starts in factory programmed, internal configuration code. this kernel is hidden and cannot be accessed by user code. if the part is in normal mode (bm pin is high), it executes the power - on configuration routine of the kernel and then jumps to the reset vector address, 0x00000000, to execute the reset exception routine of the user. because the flash/ee is mirrored at the bottom of the memory array at reset, the reset interrupt routine must always be written in flash/ee. the remap is done from flash/ee by setting bit 0 of the remap register. caution must be taken to execute this command from flash/ee, above address 0x00080020, and not fr om the bottom of the array, because this is replaced by the sram. this operation is reversible. the flash/ee can be remapped at address 0x00000000 by clearing bit 0 of the remap mmr. caution must again be taken to execute the remap function from outside th e mirrored area. any type of reset remaps the flash/ee memory at the bottom of the array. reset operation there are four kinds of reset: external, power - on, watchdog expiation, and software force. the rststa register indicates the source of the last reset , and rstclr allows clearing of the rststa register. these registers can be used during a reset exception service routine to identify the source of the reset. if rststa is null, the reset is external. the rstcfg register allows different peripherals to re tain their state after a watchdog or software reset. rststa register name: rststa address: 0xffff0230 default value: 0x01 access: read only table 60 . rststa mmr bit descriptions bit description [7:3] reserved. 2 software res et. set by the user to force a software reset. cleared by setting the corresponding bit in rstclr. 1 watchdog timeout. set automatically when a watchdog timeout occurs. cleared by setting the corresponding bit in rstclr. 0 power - on reset. set automat ically when a power - on reset occurs. cleared by setting the corresponding bit in rstclr. rstclr register name: rstclr address: 0xffff0234 default value: 0x00 access: write only note that to clear the rststa register, users must write the value 0x07 t o the rstclr register. rstcfg register name: rstcfg address: 0xffff024c default value: 0x05 access: read/write table 61 . rstcfg mmr bit descriptions bit description [7:3] reserved. always set to 0. 2 this bit is set to 1 to c onfigure the dac outputs to retain their state after a watchdog or software reset. this bit is cleared for the dac pins and registers to return to their default state. 1 reserved. always set to 0. 0 this bit is set to 1 to configure the gpio pins to re tain their state after a watchdog or software reset. this bit is cleared for the gpio pins and registers to return to their default state. the rstcfg write sequence is as follows: 1. write code 0x76 to register rstkey1. 2. write user value to register rstcfg. 3. write code 0xb1 to register rstkey2. rev. d | page 51 of 110
aduc7124/aduc7126 data sheet rstkey0 register name: rstkey0 address: 0xffff0248 default value: n/a access write only rstkey1 register name: rstkey1 address: 0xffff0250 default value: n/a access: write only rev. d | page 52 o f 110
data sheet aduc7124/aduc7126 rev. d | page 53 of 110 other analog peripherals dac the aduc7124 / aduc7126 incorporate two, or four, 12-bit voltage output dacs on chip, depending on the model. each dac has a rail-to-rail voltage output buffer capable of driving 5 k/100 pf. each dac has three selectable ranges: 0 v to v ref (internal band gap 2.5 v reference), 0 v to dac ref , and 0 v to av dd . dac ref is equivalent to an external reference for the dac. the signal range is 0 v to av dd . mmrs interface each dac is independently configurable through a control register and a data register. these two registers are identical for the four dacs. only dac0con (see table 63) and dac0dat (see table 65) are described in detail in this section. table 62. dacxcon registers name address default value access dac0con 0xffff0600 0x00 r/w dac1con 0xffff0608 0x00 r/w dac2con 0xffff0610 0x00 r/w dac3con 0xffff0618 0x00 r/w table 63. dac0con mmr bit descriptions bit value name description [7:6] reserved. 5 dacclk dac update rate. set by the user to update the dac using timer1. cleared by the user to update the dac using hclk (core clock). 4 dacclr dac clear bit. set by the user to enable normal dac operation. cleared by the user to reset the data register of the dac to 0. 3 reserved. this bit should be left at 0. 2 reserved. this bit should be left at 0. [1:0] dac range bits. 00 power-down mode. the dac output is in tristate. 01 0 v to dac ref range. 10 0 v to v ref (2.5 v) range. 11 0 v to av dd range. table 64. dacxdat registers name address default value access dac0dat 0xffff0604 0x00000000 r/w dac1dat 0xffff060c 0x00000000 r/w dac2dat 0xffff0614 0x00000000 r/w dac3dat 0xffff061c 0x00000000 r/w table 65. dac0dat mmr bit descriptions bit description [31:28] reserved. [27:16] 12-bit data for dac0. [15:0] reserved. using the dacs the on-chip dac architecture cons ists of a dac resistor string followed by an output buffer ampl ifier. the functional equivalent is shown in figure 41. 09123-023 r r r r r dac0 v ref av dd dac ref figure 41. dac structure as illustrated in figure 41, the reference source for each dac is user selectable in software. it can be either av dd , v ref , or dac ref . in 0 v-to-av dd mode, the dac output transfer function spans from 0 v to the voltage at the av dd pin. in 0 v-to-dac ref mode, the dac output transfer function spans from 0 v to the voltage at the dac ref pin. in 0 v-to-v ref mode, the dac output transfer function spans from 0 v to the internal 2.5 v reference, v ref . the dac output buffer amplifier features a true, rail-to-rail output stage implementation. this means that, when unloaded, each output is capable of swinging to within less than 5 mv of both av dd and ground. moreover, the dac linearity specification (when driving a 5 k resistive load to ground) is guaranteed through the full transfer function except the 0 to 100 codes, and, in 0 v-to-av dd mode only, code 3995 to code 4095. linearity degradation near ground and v dd is caused by satu- ration of the output amplifier, and a general representation of its effects (neglecting offset and gain error) is illustrated in figure 42. the dotted line in figure 42 indicates the ideal transfer function, and the solid line represents what the transfer function may look like with endpoint nonlinearities due to saturation of the output amplifier. note that figure 42 represents a transfer function in 0 v-to-av dd mode only. in 0 v-to-v ref or 0 v-to-dac ref mode (with v ref < av dd or dac ref < av dd ), the lower nonlinear- ity is similar. however, the upper portion of the transfer function follows the ideal line right to the end (v ref in this case, not av dd ), showing no signs of endpoint linearity errors.
aduc7124/aduc7126 data sheet 09123-024 av dd av dd ? 100mv 100mv 0x00000000 0x0fff0000 figure 42 . endpoint nonlinearities due to amplifier saturation the endpoint nonlinearities conceptually illustrated in figure 42 becomes worse as a function of output loading. most of the aduc7124 / aduc7126 data sheet specifications assume a 5 k? resistive load to ground at the dac output. as the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of figure 42 become larger. with larger current demands, this can significantly limit output voltage swing. references to adc and the dacs the adc and dacs can be configured to use the internal v ref or an external reference as a reference source. the internal v ref must work with an external 0.47 f capacitor. table 66. reference source selection for the adc and dacs refcon[0] dacxcon[1:0] description 0 00 adc works with an external reference. dacs are powered down. 0 01 adc works with an exte rnal reference. dac works with dac ref . 0 10 reserved. 0 11 adc works with an external reference. dacs work with internal av dd . 1 00 adc works with an internal v ref . dacs are powered down. 1 01 adc works with an external reference. dacs work with dac ref . 1 10 adc and dacs work with an internal v ref . 1 11 adc works with an internal v ref . dacs work with an internal av dd . note that if refcon[1] = 1, the internal v ref powers down and the adc cannot use the internal v ref . configuring dac buffers in op a mp mode in op amp mode, the dac output buffers are used as an op amp with the dac itself disabled. if dacbcfg bit 0 is set, adc0 is the positive input to the op amp, adc1 is the negative input, and dac0 is the output. in this mode, the dac should be powere d down by clearing bit 0 and bit 1 of dac0con. if dacbcfg bit 1 is set, adc2 is the positive input to the op amp, adc3 is the negative input, and dac1 is the output. in this mode, the dac should be powered down by clearing bit 0 and bit 1 of dac1con. if da cbcfg bit 2 is set, adc4 is the positive input to the op amp, adc5 is the negative input, and dac2 is the output. in this mode, the dac should be powered down by clearing bit 0 and bit 1 of dac2con. if dacbcfg bit 3 is set, adc8 is the positive input to th e op amp, adc9 is the negative input, and dac3 is the output. in this mode, the dac should be powered down by clearing bit 0 and bit 1 of dac3con. dacbcfg register name: dacbcfg address: 0xffff0654 default value: 0x00 access: read/write table 67 . dacbcfg mmr bit descriptions bit description [7:4] reserved. always set to 0. 3 set this bit to 1 to configure the dac3 output buffer in op amp mode. clear this bit for the dac buffer to operate as normal. 2 set this bit to 1 to co nfigure the dac2 output buffer in op amp mode. clear this bit for the dac buffer to operate as normal. 1 set this bit to 1 to configure the dac1 output buffer in op amp mode. clear this bit for the dac buffer to operate as normal. 0 set this bit to 1 to configure the dac0 output buffer in op amp mode. clear this bit for the dac buffer to operate as normal. the dacbcfg write sequence is as follows: 1. write code 0x9a to register dacbkey1. 2. write user value to register dacbcfg. 3. write code 0x0c to register dacb key2. rev. d | page 54 o f 110
data sheet aduc7124/aduc7126 rev. d | page 55 of 110 dacbkey1 register name: dacbkey1 address: 0xffff0650 default value: 0x0000 access: write dacbkey2 register name: dacbkey2 address: 0xffff0658 default value: 0x0000 access: write power supply monitor the power supply monitor regulates the iov dd supply on the aduc7124/ aduc7126 . it indicates when the iov dd supply pin drops below one of two supply trip points. the monitor function is controlled via the psmcon register. if enabled in the irqen or fiqen register, the monitor interrupts the core using the psmi bit in the psmcon mmr. this bit is immediately cleared when cmp goes high. this monitor function allows the user to save working registers to avoid possible data loss due to low supply or brown-out conditions. it also ensures that normal code execution does not resume until a safe supply level is established. psmcon register name: psmcon address: 0xffff0440 default value: 0x0008 access: read/write table 68. psmcon mmr bit descriptions bit name description 3 cmp comparator bit. this is a read-only bit that directly reflects the state of the comparator. read 1 indicates that the iov dd supply is above its selected trip point or that the psm is in power-down mode. read 0 indicates that the iov dd supply is below its selected trip point. this bit should be set before leaving the interrupt service routine. 2 tp trip point selection bits. 0 = 2.79 v, 1 = 3.07 v. 1 psmen power supply monitor enable bit. set to 1 to enable the power supply monitor circuit. clear to 0 to disable the power supply monitor circuit. 0 psmi power supply monitor interru pt bit. this bit is set high by the microconverter when cmp goes low, indicating low i/o supply. the psmi bit can be used to interrupt the processor. when cmp returns high, the psmi bit can be cleared by writing a 1 to this location. a 0 write has no effect. there is no timeout delay; psmi can be immediately cleared when cmp goes high. comparator the aduc7124 / aduc7126 integrate a voltage comparator. the positive input is multiplexed with adc2, and the negative input has two options: adc3 or dac0. the output of the comparator can be configured to generate a system interrupt, be routed directly to the programmable logic array, start an adc conver- sion, or be on an external pin, cmp out , as shown in figure 43. 09123-225 mux irq mux dac0 adc2/cmp0 adc3/cmp1 p0.0/cmp out figure 43. comparator hysteresis figure 44 shows how the input o ffset voltage and hysteresis terms are defined. input offset voltage (v os ) is the difference between the center of the hysteres is range and the ground level. this can either be positive or negative. the hysteresis voltage (v h ) is ? the width of the hysteresis range. 09123-063 cmp out comp0 v h v h v os figure 44. comparator hysteresis transfer function
aduc7124/aduc7126 data sheet comparator interface the comparator interface consists of a 16 - bit mmr, cmpcon, which is described in table 69 . cmpcon register name: cmpcon address: 0xffff0444 default value: 0x0000 access: read/write table 69 . cmpcon mmr bit descriptions bit value name description [15:11] reserved. 10 cmpen comparator enable bit. set by the user to enable the comparator. cleared by th e user to disable the comparator. [9:8] cmpin comparator negative input select bits. 00 av dd /2. 01 adc3 input. 10 dac0 output. 11 reserved. [7:6] cmpoc comparator output configuration bits. 00 reserved. 01 reserved. 10 output on cm p out . 11 irq. 5 cmpol comparator output logic state bit. when low, the comparator output is high if the positive input (cmp0) is above the negative input (cmp1). when high, the comparator output is high if the positive input is below the negative inpu t. [4:3] cmpres response time. 00 5 s response time typical for large signals (2.5 v differential). 17 s response time typical for small signals (0.65 mv differential). 11 4 s typical. 01/10 reserved. 2 cmphyst comparator hysteresis sit. s et by user to have a hysteresis of about 7.5 mv. cleared by user to have no hysteresis. bit value name description 1 cmpori comparator output rising edge interrupt. set automatically when a rising edge occurs on the moni tored voltage (cmp0). cleared by user by writing a 1 to t his bit. 0 cmpofi comparator output falling edge interrupt. set automatically when a falling edge occurs on the monitored voltage (cmp0). cleared by user by writing a 1 to this bit. oscillator and pll power control clocking system the aduc7124 / aduc7126 integrate a 32.768 khz 3% oscilla - tor, a clock divider, and a pll. the pll locks onto a multiple (1275) of the i nternal oscillator or an external 32.768 khz crystal to provide a stable 41.78 mhz clock (uclk) for the system. to allow power saving, the core can operate at this frequency or at binary submultiples of it. the actual core operating frequency, uclk/2 cd , is referred to as hclk. the default core clock is the pll clock divided by 8 (cd = 3) or 5.22 mhz. the core clock frequency can also come from an external clock on the eclk pin as shown in figure 45 . the core clock can be output on eclk when using an internal oscillator or external crystal. note that, when the eclk pin is used to output the core clock, the output signal is not buffered and is not suitable for use as a clock source to an external device without an e xternal buffer. 09123-126 *32.768khz 3% at power up 41.78mhz oclk 32.768khz watchdog timer int. 32khz* oscillator crystal oscillator wakeup timer mdclk hclk pll core i 2 c uclk analog peripherals /2 cd cd xclko xclki xclk eclk figure 45 . clocking system the selection of the clock source is in the pllcon register. by default, the part uses the internal oscillator feeding the pll. rev. d | page 56 o f 110
data sheet aduc7124/aduc7126 external crystal selection to switch to an external cry stal, the user must follow this procedure: 1. enable the timer2 interrupt and configure it for a timeout period of >120 s. 2. follow the write sequence to the pllcon register, setting the mdclk bits to 01 and clearing the osel bit. 3. force the part into nap mode by following the correct write sequence to the powcon0 register. 4. when the part is interrupted from nap mode by the timer2 interrupt source, the clock source has switched to the external clock. example source code: t2ld = 5; t2con = 0x480; irqen = 0x10; //enable t2 interrupt pllkey1 = 0xaa; pllcon = 0x01; pllkey2 = 0x55; powkey1 = 0x01; powcon0 = 0x27; // set core into nap mode powkey2 = 0xf4; in noisy environments, noise can couple to the external crystal pins, and pll may lose lock momentarily . a pll interrupt is provided in the interrupt controller. the core clock is immediately halted, and this interrupt is serviced only when the lock is restored. in case of crystal loss, the watchdog timer shou ld be used. during initialization, a test on the rststa can determine if the reset came from the watchdog timer. external clock selection to switch to an external clock on p0.7, configure p0.7 in mode 1. the external clock can be up to 41.78 mhz, providin g the tolerance is 1%. example source code: t2ld = 5; t2con = 0x480; irqen = 0x10; //enable t2 interrupt pllkey1 = 0xaa; pllcon = 0x03; //select external clock pllkey2 = 0x55; powkey1 = 0x01; powcon0 = 0x27; // set core into nap mode powkey2 = 0xf4; power control system a choice of operating modes is available on the aduc7124 / aduc7126 . table 70 describes what part is powered on in the different modes and indicates the power - up time. table 71 gives some typica l values of the total current consumption (analog + digital supply currents) in the different modes, depending on the clock divider bits. the ac, dac, i 2 c, and spi are turned off. table 70 . operating modes mode core peripherals pl l xtal/t2/t3 irq0 to irq3 start - up/power - on time active on on on on on 66 ms at cd = 0 pause on on on on 2.6 s at cd = 0; 247 s at cd = 7 nap on on on 2.6 s at cd = 0; 247 s at cd = 7 sleep on on 1.58 ms stop on 1.7 ms table 71 . typical current consumption at 25c in ma, v dd = 3.3 v mode cd = 0 cd = 1 cd = 2 cd = 3 cd = 4 cd = 5 cd = 6 cd = 7 active 33.3 23.1 15.4 11.6 9.7 8.8 8.3 8.1 pause 20.6 12.7 8.8 6.8 5.8 5.3 5.1 4.9 nap 4.6 4.6 4.6 4.6 4.6 4.6 4.6 4.6 sleep 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 stop 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 rev. d | page 57 of 110
aduc7124/aduc7126 data sheet mmrs and keys the operating mode, clocking mode, and programmable clock divider are controlled via three mmrs, pllcon (see table 73 ), and powconx. pllcon controls the operating mode of the clock system, powcon0 controls the core clock frequency and the power - down mode, and powcon1 controls the clock frequency to i 2 c and spi. table 72 . pllkeyx registers name a ddress default value access pllkey1 0xffff0410 0x0000 w pllkey2 0xffff0418 0x0000 w pllcon register name: pllcon address: 0xffff0414 default value: 0x21 access: read/write table 73 . pllcon mmr bit descriptions bit value name description [7:6] reserved. 5 osel 32 khz pll input selection. set by the user to select the internal 32 khz oscillator. set by default. cleared by the user to select the external 32 khz crystal. [4:2] reserved. [1:0] mdclk clocking modes. 0 0 reserved. 01 pll. default configuration. 10 reserved. 11 external clock on the p0.7 pin. to prevent accidental programming, a certain sequence must be followed to write to the pllcon register.the pllcon write sequence is as follows: 1. write c ode 0xaa to register pllkey1. 2. write user value to register pllcon. 3. write code 0x55 to register pllkey2. table 74 . powkeyx registers name address default value access powkey1 0xffff0404 0x0000 w powkey2 0xffff040c 0x0000 w powkey1 a nd powkey2 are used to prevent accidental programming to powcon0. powcon0 register name: powcon0 address: 0xffff0408 default value: 0x0003 access: read/write table 75 . powcon0 mmr bit descriptions bit value name description 7 reserved. [6:4] pc operating modes. 000 active mode. 001 pause mode. 010 nap mode. 011 sleep mode. irq0 to irq3 and timer2 can wake up the part. 100 stop mode. irq0 to irq3 can wake up the part. others reserved. 3 reserved. [2:0] cd cpu clock divider bits. 000 41.78 mhz. 001 20.89 mhz. 010 10.44 mhz. 011 5.22 mhz. 100 2.61 mhz. 101 1.31 mhz. 110 653 khz. 111 326 khz. to prevent accidental programming, a certain sequence must be followed to write to the pow conx register. the powcon0 write sequence is as follows: 1. write code 0x01 to register powkey1. 2. write a user value to register powcon0. 3. write code 0xf4 to register powkey2. table 76 . powkeyx registers name address default value acces s powkey3 0xffff0434 0x0000 w powkey4 0xffff043c 0x0000 w powkey3 and powkey4 are used to prevent accidental programming to powcon1. powcon1 register name: powcon1 address: 0xffff0438 default value: 0x124 access: read/write rev. d | page 58 o f 110
data sheet aduc7124/aduc7126 table 77 . powcon1 mmr bit descriptions 1 bit value name description [15:12] reserved. 11 1 pwmpo clearing this bit powers down the pwm. always clear to 00. [10:9] 00 pwmclkdiv 8 spipo clearing this bit powers down the spi. [7:6] spiclkdiv spi bl ock driving clock divider bits. 00 41.78 mhz. 01 20.89 mhz. 10 10.44 mhz. 11 5.22 mhz. 5 i2c 1 po clearing this bit powers down i2c 1 . [4:3] i2c 1 clkdiv i2c0 block driving clock divider bits. 00 41.78 mhz. 01 10.44 mhz. 10 5.22 mhz. 11 1.31 mhz. 2 i2c 0 po clearing this bit powers down i2c 0 . [1:0] i2c 0 clkdiv i2c1 block driving clock divider bits. 00 41.78 mhz. 01 10.44 mhz. 10 5.22 mhz. 11 1.31 mhz. the powcon1 write sequence is as follows: 1. write code 0x76 to register powkey3. 2. write user value to register powcon1. 3. write code 0xb1 to register powkey4. 1 divided clock for spi/i2c0/i2c1 must be greater than or equal to the cpu clock as selected by powcon0 [2:0] . rev. d | page 59 of 110
aduc7124/aduc7126 data sheet digital peripheral general - purpose input/output the aduc7124 / aduc7126 provide 40 general - purpose, bidirec tional i/o (gpio) pins. all i/o pins are 5 v tolerant, meaning th e gpios support an input voltage of 5 v. in general, many of the gpio pins have multiple functions (see the pin configurations and function descriptions section for pin function definitions). by default, the gpio pins are configured in gpio mode. all gpio pins have an internal pull - up resistor (of about 100 k?), and their drive capability is 1.6 ma. note that a maximum of 20 gpios can drive 1.6 ma at the same time. using the gp x pa r registers, it is possible to enable/disable the pull - up resistors for the following ports: p0.0, p0.4, p0.5, p0.6, p0.7, and the eight gpios of p1. the 40 gpios are grouped in five ports, port 0 to port 4 (port x) . each port is controlled by four or five mmrs. note that the kernel changes p0.6 from its default configuration at reset (mrst) to gpio mode. if mrst is used for exte rnal circuitry, an external pull - up resistor should be used to ensure that the level on p0.6 does not drop when the kernel switches mode. otherwise, p0.6 goes low for the reset period. for example, if mrst is required for power - down, it can be reconfigured in gp0con mmr. the input level of any gpio can be read at any time in the gpxdat mmr, even when the pin is configured in a mode other than gpio. the pla input is always active. when the aduc7124 / aduc7126 enter a power - saving mode, the gpio pins retain their state. also, note that, by setting rstcfg bit 0, the gpio pins can retain their state during a watchdog or softwa re reset. table 78 . gpio pin function descriptions configuration port pin 00 01 10 11 0 bm/p0.0 gpio cmp ms0 plai[7] tdi/p0.1 1 gpio/jtag pwm 4 ble 4 tdo/p0.2 1 gpio/jtag pwm 5 bhe 4 trst/p0.3 1 gpio/jtag trst a16 4 adc busy p0.4 gpio/irq0 pwm trip ms1 4 plao[1] p0.5 gpio/irq1 adc busy ms2 4 plao[2] p0.6 gpio mrst ms3 4 plao[3] p0.7 gpio eclk/xclk 2 sin 0 plao[4] 1 p1.0 gpio/t1 sin 0 scl0 3 plai[0] p1.1 gpio sout 0 sda0 3 plai[1] p1.2 gpio rts 3 scl1 3 plai[2] p1.3 gpio cts 3 sda1 3 plai[3] p1.4 gpio/irq2 ri 3 s clk 3 plai[4] p1.5 gpio/irq3 dcd 3 miso 3 plai[5] p1.6 gpio dsr 3 mosi 3 plai [6] p1.7 gpio dtr 3 cs 3 plao[0] 2 p2.0 gpio conv start sout 0 plao[5] p2.1 gpio pwm 0 ws 4 plao[6] p2.2 gpio pwm 1 rs 4 plao[7] p2.3 gpio ae 4 sin1 p2.4 gpio pwm 0 ms0 4 sout1 p2 .5 gpio pwm 1 ms1 4 p2.6 gpio pwm 2 ms2 4 p2.7 gpio pwm 3 ms3 4 3 p3.0 gpio pwm 0 ad0 4 plai[8] p3.1 gpio pwm 1 ad1 4 plai[9] p3.2 gpio pwm 2 ad2 4 plai[10] p3.3 gpio pwm 3 ad3 4 plai[11] p3.4 gpio pwm 4 ad4 4 plai[12] p3.5 gpio pwm 5 ad5 4 plai[13] p3.6 gpio pwm trip ad6 4 plai[14] p3.7 gpio pwm sync ad7 4 plai[15] 4 p4.0 gpio sin1 ad8 4 plao[8] p4.1 gpio sout1 ad9 4 plao[9] p4.2 gpio ad10 4 plao[10] p4.3 gpio ad11 4 plao[11] p4.4 gpio ad12 4 plao[12] p4.5 gpio/rtck 5 ad13 4 plao[13] p4.6 gpio ad14 4 plao[14] p4.7 gpio ad15 4 plao[15] 1 these pins should not be used by user code . 2 when configured in mode 1, p0.7 is eclk by default, or core clock output. to configure it as a clock input, the mdclk bits in pllcon must be set to 11. 3 see table 90 for spm configurations. 4 external memory interface signals are only availab le on aduc7126 . 5 in debug mode , the rtck mode cannot be disabled. rev. d | page 60 o f 110
data sheet aduc7124/aduc7126 table 79 . gpxcon registers name address default value access gp0con 0xfffff400 0x00000000 r/w gp1con 0xfffff404 0x00000000 r /w gp2con 0xfffff408 0x00000000 r/w gp3con 0xfffff40c 0x00000000 r/w gp4con 0xfffff410 0x00000000 r/w gpxcon are the port x control registers that select the function of each pin of port x, as described in tab le 80 . table 80 . gpxcon mmr bit descriptions bit description [31:30] reserved. [29:28] select function of px.7 pin. [27:26] reserved. [25:24] select function of px.6 pin. [23:22] reserved. [21:20] select function of px.5 pin. [19:18] reserved. [17:16] select function of px.4 pin. [15:14] reserved. [13:12] select function of px.3 pin. [11:10] reserved. [9:8] select function of px.2 pin. [7:6] reserved. [5:4] select function of px.1 pin. [3:2] reserved. [1:0] select fu nction of px.0 pin. table 81 . gpxpar registers name address default value access gp0par 0xfffff42c 0x20000000 r/w gp1par 0xfffff43c 0x00000000 r/w gp2par 0xfffff44c 0x000000ff r/w gp3par 0xfffff45c 0x00222222 r/w gp4par 0xfff ff46c 0x00000000 r/w the gpxpar registers program the parameters for port 0, port 1, port 2, port 3, and port 4. note that the gpxdat mmr must always be written after changing the gpxpar mmr. table 82 . gpxpar mmr bit descriptions b it description 31 reserved. [30:29] drive strength px.7. 28 pull - up disable px.7. 27 reserved. [26:25] drive strength px.6. 24 pull - up disable px.6. 23 reserved. [22:21] drive strength px.5. 20 pull - up disable px.5. 19 reserved. [18:17] drive st rength px.4. b it description 16 pull - up disable px.4. 15 reserved. [14:13] drive strength px.3. 12 pull - up disable px.3. 11 reserved. [10:9] drive strength px.2. 8 pull - up disable px.2. 7 reserved. [6:5] drive strength px.1. 4 pull - up disable px.1. 3 reserved. [2:1] drive strength px.0. 0 pull - up disable px.0. table 83 . gpio drive strength control bits descriptions control bits value description 00 medium drive strength. 01 low drive strength. 1x high drive strength. 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 ?24 ?18 ?12 ?6 0 6 12 18 24 sink/source current (ma) supp l y vo lt age (v) high drive strength medium drive strength low drive strength 09123-148 figure 46 . programmable strength for high level ?0.4 ?0.3 ?0.2 ?0.1 0.1 0 0.2 0.3 0.4 0.5 ?24 ?18 ?12 ?6 0 6 12 18 24 sink/source current (ma) supp l y vo lt age (v) high drive strength medium drive strength low drive strength 09123-149 figure 47 . programmable strength for low level rev. d | page 61 of 110
aduc7124/aduc7126 data sheet the drive strength bits can be written only once after reset. additional writing to related bits has no effect on drive strength. the gpio drive strength and pull - up disable are not always adjustable for gpio port. some control bits cannot be changed. see table 78 for details. table 84 . gpxdat registers nam e address default value access gp0dat 0xfffff420 0x000000xx r/w gp1dat 0xfffff430 0x000000xx r/w gp2dat 0xfffff440 0x000000xx r/w gp3dat 0xfffff450 0x000000xx r/w gp4dat 0xfffff460 0x000000xx r/w the gpxdat are port x configuration and data register s. they configure the direction of the gpio pins of port x, set the output value for the pins configured as output, and store the input value of the pins configured as input. table 85 . gpxdat mmr bit descriptions bit description [3 1:24] direction of the data. set to 1 by the user to configure the gpio pin as an output . cleared to 0 by the user to configure the gpio pin as an input. [23:16] port x data output. [15:8] reflect the state of port x pins at reset (read only). [7:0] p ort x data input (read only). table 86 . gpxset registers name address default value access gp0set 0xfffff424 0x000000xx w gp1set 0xfffff434 0x000000xx w gp2set 0xfffff444 0x000000xx w gp3set 0xfffff454 0x000000xx w gp4set 0xf ffff464 0x000000xx w the gpxset are data set port x registers. table 87 . gpxset mmr bit descriptions bit description [31:24] reserved. [23:16] data port x set bit. set to 1 by the user to set a bit on port x; also sets the corre sponding bit in the gpxdat mmr. cleared to 0 by the user; does not affect the data output. [15:0] reserved. table 88 . gpxclr registers name address default value access gp0clr 0xfffff428 0x000000xx w gp1clr 0xfffff438 0x00000 0xx w gp2clr 0xfffff448 0x000000xx w gp3clr 0xfffff458 0x000000xx w gp4clr 0xfffff468 0x000000xx w the gpxclr are data clear port x registers. table 89 . gpxclr mmr bit descriptions bit description [31:24] reserved. [23:16] dat a port x clear bit. set to 1 by the user to clear a bit on port x; also clears the corresponding bit in the gpxdat mmr. cleared to 0 by the user; does not affect the data out. [15:0] reserved. serial port mux the serial port mux multiplexes the serial port peripherals (an spi, uart, and two i 2 cs) and the programmable logic array (pla) to a set of 10 gpio pins. each pin must be configured to one of its specific i/o functions as described in table 90. table 90 . spm configuration spm gpio uart uart/i 2 c/spi pla (00) (01) (10) (11) spm0 p1.0 sin0 i2c0scl plai[0] spm1 p1.1 sout0 i2c0sda plai[1] spm2 p1.2 rts i2c1scl plai[2] spm3 p1.3 cts i2c1sda plai[3] spm4 p1.4 ri sclk plai[4] spm5 p1.5 dcd miso plai[5] spm6 p1.6 dsr mosi plai[6] spm7 p1.7 dtr cs plao[0] spm8 p0.7 eclk/xclk sin0 plao[4] spm9 p2.0 conv start sout0 plao[5] spm10 p4.0 sin1 ad8 plao[8] spm11 p4.1 sout1 ad9 plao[9] spm12 p2.3 n/a ae sin1 spm13 p2. 4 pwm0 mso sout1 table 90 also details the mode for each of the spmmux pins. this configuration has to be done via the gp0con, gp1con, and gp2con mmrs. by default, these 10 pins are configured as gpios. uart ser ial interface the uart peripheral is a full - duplex, universal, asynchronous receiver/transmitter. the uart performs serial - to - parallel conver - sions on data characters received from a peripheral device and parallel - to - serial conversions on data characters r eceived from the cpu. the aduc7124 / aduc7126 has been equipped with two industry standard 16,450 type uarts (uart0 an d uart1). each uart features a fractional divider that facilitates high accu - racy baud rate generation and is equipped with a 16 - byte fifo for the transmitter and a 16 - byte fifo for the receiver. both uarts can be configured as fifo mode and non - fifo mode. the serial communication adopts an asynchronous protocol, which supports various word lengths, stop bits, and parity generation options selectable in the configuration register. rev. d | page 62 o f 110
data sheet aduc7124/aduc7126 baud rate generation there are two ways of generating the uart baud rate, us ing normal 450 uart baud rate generation and using the fractional divider. normal 450 uart baud rate generation the baud rate is a divided version of the core clock using the value in the com x div0 and com x div1 mmrs (16 - bit value, dl). dl rate baud cd = 2 16 2 mhz 78 . 41 table 91 gives some common baud rate values. table 91 . baud rate using the normal baud rate generator baud rate cd dl actual baud rate % error 9600 0 0x88 9600 0 19,200 0 0x44 19,200 0 115,200 0 0x0b 118,691 3 9600 3 0x11 9600 0 19,200 3 0x08 20,400 6.25 115,200 3 0x01 163,200 41.67 the fractional divider the fractional divider, combined with the normal baud rate generator, produces a wider range of more accurate baud rates. 09123-032 16dl uart fben core clock 2 (m + n 2048) fi gure 48 . baud rate generation options calculation of the baud rate using fractional divider is as follows: ? ? ? ? ? ? + = 2048 2 16 2 mhz 78 . 41 n m dl rate baud cd mh 7 . = + dl rate baud n m cd for eale generation of aud ith cd its = tale gies dl = is mh 7 . = + n m . = + n m here m = 1. n = 0.06 2048 = 128. ? ? ? ? ? ? = 2048 128 2 8 16 2 mhz 78 . 41 3 rate baud here baud rate = 19,200 bps. error is 0%, compared to 6.25% with the normal baud rate ge nerator. uart register definitions com0tx register name: com0tx address: 0xffff0700 default value: 0x00 access: read/write com0tx is an 8 - bit transmit register for uart0. com1tx register name: com1tx address: 0xffff0740 default value: 0x00 access: r ead/write com1tx is an 8 - bit transmit register for uart1. com0rx register name: com0rx address: 0xffff0700 default value: 0x00 access: read only com0rx is an 8 - bit receive register for uart0. com1rx register name: com1rx address: 0xffff0740 default value : 0x00 access: read only com1rx is an 8 - bit receive register for uart1. com0div0 register name: com0div0 address: 0xffff0700 default value: 0x00 access: read/write com0div0 is a low byte divisor latch for uart0. com0tx, com0rx, and com0div0 shar e the same address location. com0tx and com0rx can be accessed when bit 7 in the com0con0 register is cleared. com0div0 can be accessed when bit 7 of com0con0 is set. rev. d | page 63 of 110
aduc7124/aduc7126 data sheet com1div0 register name: com1div0 address: 0xffff0740 default value: 0x00 access: read /write com1div0 is a low byte divisor latch for uart1. com1tx, com1rx, and com1div0 share the same address location. com1tx and com1rx can be accessed when bit 7 in com1con0 register is cleared. com1div0 can be accessed when bit 7 of com1con0 is set. com0 ien0 register name: com0ien0 address: 0xffff0704 default value: 0x00 access: read/write com0ien0 is the interrupt enable register for uart0. com1ien0 register name: com1ien0 address: 0xffff0744 default value: 0x00 access: read/write com1ien0 is the interrupt enable register for uart1. table 92 . comxien0 mmr bit descriptions bit name description [7:4] reserved. 3 edssi modem status interrupt enable bit. set by the user to enable generation of an interrupt if any of comxsta 1[3:1] are set. cleared by the user. 2 elsi rx status interrupt enable bit. set by the user to enable generation of an interrupt if any of comxsta0[3:0] are set. cleared by the user. 1 etbei enable transmit buffer empty interrupt. set by the user to en able interrupt when the buffer is empty during a transmission. cleared by the user. 0 erbfi enable receive buffer full interrupt. in non - fifo mode, set by the user to enable an interrupt when buffer is full during a reception. cleared by the user. in fi fo mode, set by the user to enable an interrupt when trigger level is reached. it also controls the character receive timeout interrupt. cleared by the user. com0div1 register name: com0div1 address: 0xffff0704 default value: 0x00 access: read/write com0div1 is a divisor latch (high byte) register for uart0. com1div1 register name: com1div1 address: 0xffff0744 default value: 0x00 access: read/write com1div1 is a divisor latch (high byte) register for uart1. com0iid0 register name: com0iid0 addres s: 0xffff0708 default value: 0x01 access: read only com0iid0 is the interrupt identification register for uart0. it also indicates if the uart is in fifo mode. com1iid0 register name: com1iid0 address: 0xffff0748 default value: 0x01 access: read only com1iid0 is the interrupt identification register for uart1. it also indicates if the uart is in fifo mode. rev. d | page 64 o f 110
data sheet aduc7124/aduc7126 table 93 . comxiid0 mmr bit descriptions bit name description [7:6] fifomode fifo mode flag. 0x0: non - fifo mode. 0x 1: reserved. 0x2: reserved. 0x3: fifo mode. set automatically if fifoen is set. [5:4] reserved [3:1] status[2:0] interrupt status bits that work only when nint is set. [000]: modem status interrupt. cleared by reading comxsta1. priority 4. [001]: for non - fifo mode, transmit buffer empty interrupt. for fifo mode, tx fifo is empty. cleared by writing comxtx or reading comxiid0. priority 3. [010]: non - fifo mode. receive buffer data ready interrupt. cleared automatically by reading comxrx. for fifo mode, set trigger level reached. cleared automatically when fifo drops below the trigger level. priority 2. [011]: receive line status error interrupt. cleared by reading comxsta0. priority 1. [110]: rx fifo timeout interrupt (fifo mode only). set automat ically if there is at least one byte in the rx fifo, and there is no access to the rx fifo in the next four - frames accessing cycle. cleared by reading comxrx, setting rxrst, or when a new byte arrives in the rx fifo 1 . priority 2. [other state]: reserved. 0 nint set to disable interrupt flags by status[2:0]. clear to enable interrupt. 1 a frame time is the time allotted for one start bit, n data bits, one parity bit, and one stop bit. here, n is the word length selected with the wls bits in comxcon0. wl s[1:0] = 00: timeout threshold = time for 32 bits = (1 + 5 + 1 + 1) 4. wls[1:0] = 01: timeout threshold = time for 36 bits = (1 + 6 + 1 + 1) 4. wls[1:0] = 10: timeout threshold = time for 40 bits = (1 + 7 + 1 + 1) 4. wls[1:0] = 11: timeout threshold = time for 44 bits = (1 + 8 + 1 + 1) 4. com0fcr register name: com0fcr address: 0xffff0708 default value: 0x00 access: read/write the fifo control register (fcr) is a write - only register at the same address as the interrupt identification register (i ir), which is a read - only register. com1fcr register name: com1fcr address: 0xffff0748 default value: 0x00 access: read/write the fifo control register (fcr) is a write - only register at the same address as the interrupt identification register (iir), which is a read - only register. table 94 . comxfcr mmr bit descriptions bit name description [7:5] rxfifotl receiver fifo trigger level. rxfifotl sets the trigger level for the receiver fifo. when the trigger level is reached, a re ceiver data - ready interrupt is generated (if the interrupt request is enabled). when the fifo drops below the trigger level, the interrupt is cleared. 0x0: one byte. 0x1: two bytes. 0x2: four bytes. 0x3: six bytes. 0x4: eight bytes. 0x5: 10 bytes. 0x6: 12 bytes. 0x7: 14 bytes. [4:3] reserved 2 txrst tx fifo reset. writing a 1 flushes the tx fifo. does not affect shift register. note that txrst should be cleared manually to make tx fifo work after flushing. 1 rxrst rx fifo reset. writing a 1 flushes the rx fifo. does not affect shift register. note that rxrst should be cleared manually to make the rx fifo work after flushing. 0 fifoen transmitter and receiver fifos mode enable. fifoen must be set before other fcr bits are written to. set for fifo mode. the transmitter and receiver fifos are enabled. cleared for non - fifo mode; the transmitter and receiver fifos are disabled, and the fifo pointers are cleared. com0con0 register name: com0con0 address: 0xffff070c default value: 0x 00 access: read/write com0con0 is the line control register for uart0. rev. d | page 65 of 110
aduc7124/aduc7126 data sheet com1con0 register name: com1con0 address: 0xffff074c default value: 0x00 access: read/write com1con0 is the line control register for uart1. table 95 . com xcon0 mmr bit descriptions bit name description 7 dlab divisor latch access. set by the user to enable access to the comxdiv0 and comxdiv1 registers. cleared by the user to disable access to comxdiv0 and comxdiv1 and enable access to comxrx and comxtx. 6 brk set break. set by the user to force soutx to 0. cleared to operate in normal mode. 5 sp stick parity. set by the user to force parity to defined values: 1 if eps = 1 and pen = 1, 0 if eps = 0 and pen = 1. 4 eps even parity select bit. set for even parity. cleared for odd parity. 3 pen parity enable bit. set by the user to transmit and check the parity bit. cleared by the user for no parity transmission or checking. 2 stop stop bit. set by the user to transmit 1? stop bits if the word len gth is five bits or two stop bits if the word length is six bits, seven bits, or eight bits. the receiver checks the first stop bit only, regardless of the number of stop bits selected. cleared by the user to generate one stop bit in the transmitted data. [1:0] wls word length select: 00 = five bits, 01 = six bits, 10 = seven bits, 11 = eight bits. com0con1 register name: com0con1 address: 0xffff0710 default value: 0x00 access: read/write com0con1 is the modem control register for uart0. com1con1 re gister name: com1con1 address: 0xffff0750 default value: 0x00 access: read/write com1con1 is the modem control register for uart1. table 96 . comxcon1 mmr bit descriptions bit name description [7:5] reserved. 4 loopback loop b ack. set by the user to enable loopback mode. in loopback mode, soutx is forced high. the modem signals are also directly con - nected to the status inputs (rts to cts and dtr to dsr). cleared by the user to be in normal mode. 3 pen parity enable bit. set by the user to transmit and check the parity bit. cleared by the user for no parity transmission or checking. 2 stop stop bit. set by the user to transmit 1? stop bits if the word length is five bits or two stop bits if the word length is six bits, seven bits, or eight bits. the receiver checks the first stop bit only, regardless of the number of stop bits selected. cleared by the user to generate one stop bit in the transmitted data. 1 rts request to send. set by the user to force the rts output to 0. cleared by the user to force the rts output to 1. 0 dtr data terminal ready. set by the user to force the dtr output to 0. cleared by the user to force the dtr output to 1. com0sta0 register name: com0sta0 address: 0xffff0714 default value: 0 xe0 access: read only com0sta0 is the line status register for uart0. rev. d | page 66 o f 110
data sheet aduc7124/aduc7126 com1sta0 register name: com1sta0 address: 0xffff0754 default value: 0xe0 access: read only com1sta0 is the line status register for uart1. table 97 . comxst a0 mmr bit descriptions bit name description 11 rx_error set automatically if pe, fe, or bi is set. cleared automatically when pe, fe, and bi are cleared . 10 rx_timeout only for fifo mode. set automatically if there is at least one byte in the rx fifo a nd there is no access to the rx fifo in the next 4 - byte accessing cycle. 9 rx_triggered only for fifo mode. set automatically if the rx fifo number exceeds the trigger level, which is configured by the fifo control register comxfcr[7:5]. cleared automati cally when the rx fifo number is equal to or less than the trigger level. 8 tx_full only for fifo mode. set automatically if tx fifo is full. cleared automatically when tx fifo is not full. 7 tx_half_empty only for fifo mode. set automatically if the tx fifo is half empty (number of bytes in tx fifo 8). cleared automati - cally when the tx fifo received bytes is more than eight bytes. 6 temt comxtx empty status bit. for non - fifo mode, both thr and tsr are empty. for fifo mode, both tx fifo and tsr are e mpty. 5 thre comxtx and transmitter shift register empty. for non - fifo mode, transmitter hold register (thr) empty or the content of thr has been transferred to the transmitter shift register (tsr). for fifo mode, tx fifo is empty, or the last character in the fifo has been transferred to the transmitter shift register (tsr). 4 bi break error. set when sinx is held low for more than the maximum word length. cleared automatically. 3 fe framing error. set when an invalid stop bit occurs. cleared autom atically. 2 pe parity error. set when a parity error occurs. cleared automatically. bit name description 1 oe overrun error. for non - fifo mode, set automatically if data is overwritten before being read. cleared automatically. for fifo mode, set automatically if an overru n error has been detected. an overrun error occurs only after the fifo is full and the next character has been completely received in the shift register. the new character overwrites the character in the shift register, but it is not transferred to the fif o. 0 dr data ready. for non - fifo mode, set automatically when comxrx is full. cleared by reading comxrx. for fifo mode, set automatically when there is at least one unread byte in the comxrx. com0sta1 register name: com0sta1 address: 0xffff0718 defau lt value: 0x00 access: read only com0sta1 is a modem status register. com1sta1 register name: com1sta1 address: 0xffff0758 default value: 0x00 access: read only com1sta1 is a modem status register. table 98 . comxsta1 mmr bit d escriptions bit name description 7 dcd data carrier detect. 6 ri ring indicator. 5 dsr data set ready. 4 cts clear to send. 3 ddcd delta dcd. set automatically if dcd changed state since last comxsta1 read. cleared automatically by reading comxsta1. 2 teri trailing edge ri. set if ri changed from 0 to 1 since comxsta1 last read. cleared automatically by reading comxsta1. 1 ddsr delta dsr. set automatically if dsr changed state since comxsta1 last read. cleared automatically by reading comxsta1. 0 dc ts delta cts. set automatically if cts changed state since comxsta1 last read. cleared automatically by reading comxsta1. rev. d | page 67 of 110
aduc7124/aduc7126 data sheet rev. d | page 68 of 110 com0div2 register name: com0div2 address: 0xffff072c default value: 0x0000 access: read/write com0div2 is a 16-bit fractional baud divide register for uart0. com1div2 register name: com1div2 address: 0xffff076c default value: 0x0000 access: read/write com1div2 is a 16-bit fractional baud divide register for uart1. table 99. comxdiv2 mmr bit descriptions bit name description 15 fben fractional baud rate generator enable bit. set by the user to en able the fractional baud rate generator. cleared by the user to generate the baud rate using the standard 450 uart baud rate generator. [14:13] reserved. [12:11] fbm[1:0] m if fbm = 0, m = 4 (see the fractional divider section). [10:0] fbn[10:0] n (see the fractional divider section). serial peripheral interface the aduc7124 / aduc7126 integrate a complete hardware serial peripheral interface (spi) on chip. spi is an industry standard, synchronous serial interface that allows eight bits of data to be synchronously transmitted and simultaneously received, that is, full duplex up to a maximum bit rate of 20 mbps. the spi port can be configured for master or slave operation and typically consists of four pins: miso, mosi, sclk, and cs . miso (master in, slave out) pin the miso pin is configured as an input line in master mode and an output line in slave mode. the miso line on the master (data in) should be connected to the miso line in the slave device (data out). the data is transferred as byte wide (8-bit) serial data, msb first. mosi (master out, slave in) pin the mosi pin is configured as an output line in master mode and an input line in slave mode. the mosi line on the master (data out) should be connected to the mosi line in the slave device (data in). the data is transferred as byte wide (8-bit) serial data, msb first. sclk (serial clock i/o) pin the master serial clock (sclk) synchronizes the data being transmitted and received through the mosi sclk period. therefore, a byte is transmitted/received after eight sclk periods. the sclk pin is configured as an output in master mode and as an input in slave mode. in master mode, polarity and phase of the clock are controlled by the spicon register, and the bit rate is defined in the spidiv register as follows: )1(2 spidiv f f uclk clock serial ?? ? the maximum speed of the spi clock is independent of the clock divider bits. in slave mode, the spicon register must be configured with the phase and polarity of the expected input clock. the slave accepts data from an external master up to 10 mbps. in both master and slave modes, data is transmitted on one edge of the sclk signal and sampled on the other. therefore, it is important that the polarity and phase be configured the same for the master and slave devices. cs (spi chip select input) pin in spi slave mode, a transfer is initiated by the assertion of cs , which is an active low input signal. the spi port then transmits and receives 8-bit data until the transfer is concluded by deasser- tion of cs . in slave mode, cs is always an input. in spi master mode, the cs is an active low output signal. it asserts itself automatically at the beginning of a transfer and deasserts itself upon completion. configuring external pins for spi functionality the spi pins of the aduc7124/ aduc7126 device are p1.4 to p1.7. p1.7 is the slave chip select pin. in slave mode, this pin is an input and must be driven low by the master. in master mode, this pin is an output and goes lo w at the beginning of a transfer and high at the end of a transfer. p1.4 is the sclk pin. p1.5 is the master in, slave out (miso) pin. p1.6 is the master out, slave in (mosi) pin. to configure p1.4 to p1.7 for spi mode, see the general- purpose input/output section.
data sheet aduc7124/aduc7126 rev. d | page 69 of 110 spi registers the following mmr registers control the spi interface: spista, spirx, spitx, spidiv, and spicon. spi status register name: spista address: 0xffff0a00 default value: 0x0000 access: read only function: this 32-bit mmr contains the status of the spi interface in both master and slave modes. table 100. spista mmr bit descriptions bit name description [15:12] reserved. 11 spirex spi rx fifo excess bytes present. this bit is set when th ere are more bytes in the rx fifo than indicated in the spimde bits in spicon this bit is cleared when the number of bytes in th e fifo is equal to or less than the number in spimde. [10:8] spirxfsta[2:0] spi rx fifo status bits. [000] = rx fifo is empty. [001] = one valid byte in the fifo. [010] = two valid bytes in the fifo. [011] = three valid bytes in the fifo. [100] = four valid bytes in the fifo. 7 spifof spi rx fifo overflow status bit. set when the rx fifo was already full when new data was loaded to the fifo. this bit generates an interrupt except when spirflh is set in spicon. cleared when the spista register is read. 6 spirxirq spi rx irq status bit. set when a receive interrupt occurs. this bit is set when spitmde in spicon is cleared and the required number of bytes has been received. cleared when the spista register is read. 5 spitxirq spi tx irq status bit. set when a transmit interrupt occurs. this bit is set wh en spitmde in spicon is set and the required number of bytes has been transmitted. cleared when the spista register is read. 4 spitxuf spi tx fifo underflow. this bit is set when a transmit is initiated without any va lid data in the tx fifo. this bit generates an interrupt except when spitflh is set in spicon. cleared when the spista register is read. [3:1] spitxfsta[2:0] spi tx fifo status bits. [000] = tx fifo is empty. [001] = one valid byte in the fifo. [010] = two valid bytes in the fifo. [011] = three valid bytes in the fifo. [100] = four valid bytes in the fifo. 0 spiista spi interrupt status bit. set to 1 when an spi-based interrupt occurs. cleared after reading spista.
aduc7124/aduc7126 data sheet spirx register name: spirx address: 0xffff0a04 defaul t value : 0x00 access: read only function: this 8 - bit mmr is the spi receive register. spitx register name: spitx address: 0xffff0a08 default value : 0x00 access: write only function: this 8 - bit mmr is the spi transmit register. spidiv register name : spidiv address: 0xffff0a0c default value : 0x00 access: read/write function: this 8 - bit mmr is the spi baud rate selection register. spicon register name: spicon address: 0xffff0a10 default value : 0x0000 access: read/write function: this 16 - bit m mr configures the spi peripheral in both master and slave modes. table 101 . spicon mmr bit descriptions bit name description [15:14] spimde spi irq mode bits. these bits configure when the tx/rx interrupts occur in a transfer. [00] = tx interrupt occurs when one byte has been transferred. rx interrupt occurs when one or more bytes have been received into the fifo. [01] = tx interrupt occurs when two bytes have been transferred. rx interrupt occurs when two or more bytes hav e been received into the fifo. [10] = tx interrupt occurs when three bytes have been transferred. rx interrupt occurs when three or more bytes have been received into the fifo. [11] = tx interrupt occurs when four bytes have been transferred. rx interrupt occurs when the rx fifo is full or four bytes are present. 13 spitflh spi tx fifo flush enable bit. set this bit to flush the tx fifo. this bit does not clear itself and should be toggled if a single flush is required. if this bit is left high, then e ither the last transmitted value or 0x00 is transmitted, depending on the spizen bit. any writes to the tx fifo are ignored while this bit is set. clear this bit to disable tx fifo flushing. 12 spirflh spi rx fifo flush enable bit. set this bit to f lush the rx fifo. this bit does not clear itself and should be toggled if a single flush is required. if this bit is set incoming, data is ignored and no interrupts are generated. if set and spitmde = 0, a read of the rx fifo initiates a transfer. clear this bit to disable rx fifo flushing. 11 spicont continuous transfer enable. set by the user to enable continuous transfer. in master mode, the transfer continues until no valid data is available in the spitx register. cs is asserted and remains asserted for the duration of each 8 - bit serial transfer until spitx is empty. cleared by the user to disable continuous transfer. each transfer consists of a single 8 - bit serial transfer. if valid data exists in the spitx register, then a n ew transfer is initiated after a stall period of one serial clock cycle. 10 spilp loopback enable bit. set by the user to connect miso to mosi and test software. cleared by the user to be in normal mode. rev. d | page 70 o f 110
data sheet aduc7124/aduc7126 bit name description 9 spioen slave miso output enable bit. s et this bit for miso to operate as normal. clear this bit to disable the output driver on the miso pin. the miso pin is open - drain when this bit is cleared. 8 spirow spirx overflow overwrite enable. set by the user, the valid data in the spirx regi ster is overwritten by the new serial byte received. cleared by the user, the new serial byte received is discarded. 7 spizen spi transmits zeros when tx fifo is empty. set this bit to transmit 0x00 when there is no valid data in the tx fifo. cle ar this bit to transmit the last transmitted value when there is no valid data in the tx fifo. 6 spitmde spi transfer and interrupt mode. set by the user to initiate transfer with a write to the spitx register. interrupt occurs only when spitx is empty . cleared by the user to initiate transfer with a read of the spirx register. interrupt occurs only when spirx is full. 5 spilf lsb first transfer enable bit. set by the user, the lsb is transmitted first. cleared by the user, the msb is transmi tted first. 4 spiwom spi wire - ored mode enable bit. set to 1 enable open - drain data output. external pull - ups required on data output pins. cleared for normal output levels. 3 spicpo serial clock polarity mode bit. set by the user, the serial clock idles high. cleared by the user, the serial clock idles low. 2 spicph serial clock phase mode bit. set by the user, the serial clock pulses at the beginning of each serial bit transfer. cleared by the user, the serial clock pulses at the en d of each serial bit transfer. 1 spimen master mode enable bit. set by the user to enable master mode. cleared by the user to enable slave mode. 0 spien spi enable bit. set by the user to enable the spi . cleared by the user to disable the sp i. rev. d | page 71 of 110
aduc7124/aduc7126 data sheet i 2 c the aduc7124 / aduc7126 incorporate two i 2 c peripherals that can be configured as a fully i 2 c - compatible i 2 c bus master device or as a fully i 2 c bus compatible slave device. both i 2 c channels are identical. therefore, the following descriptions apply to both channels . the two pins used for data transfer, sda and scl, are configured in a wire - anded format that allows arbitration in a multimaster system. these pins require external pull - up resistors. typical pull - up values are between 4.7 k? and 10 k?. the i 2 c bus peripheral address in the i 2 c bus system is programmed by the user. this id can be modified any tim e a transfer is not in progress. the user can configure the interface to respond to four slave addresses. the transfer sequence of an i 2 c system consists of a master device initiating a transfer by generating a start condition while the bus is idle. the ma ster transmits the slave device address and the direction of the data transfer (read or/write) during the initial address transfer. if the master does not lose arbitration and the slave acknowledges, the data transfer is initiated. this continues until the master issues a stop condition and the bus becomes idle. the i 2 c peripheral can only be configured as a master or slave at any given time. the same i 2 c channel cannot simultaneously support master and slave modes. the i 2 c interface on the aduc7124 / aduc7126 includes the following features: ? support for repeated start conditions. in master mode, the aduc7124 / aduc7126 can be programmed to generate a repeated start. in slave mode, the aduc7124 / aduc7126 recognizes repeated start conditions. ? in master and slave mode, the part recognizes both 7 - bit and 10 - bit bus addresses. ? in i 2 c master mode, the aduc7124 / aduc7126 supports continuous reads from a single slave up to 512 bytes in a single transfer sequence. ? clock stret ching can be enabled by other devices on the bus without causing any issues with th e aduc7124 / aduc7126 . however, th e aduc7124 / aduc7126 cannot enable clock stretching . ? in slave mode, the aduc7124 / aduc7126 can be pro - grammed to return a nack. this allows the validiation of checksum bytes at the end of i 2 c transfers. ? bus arbitration in master mode is supported. ? internal and external loopback modes are supported for i 2 c hardware testing in loopback mode. ? the transmit and receive circuits in both master and slave mode contain 2 - byte fifos. status bits are available to the user to control these fifos. configuring external pins for i 2 c functionality the i 2 c pins of the aduc7124 / aduc7126 device are p1.0 and p1.1 for i2c0 and p1.2 and p1.3 for i2c1. p1.0 and p1.2 are the i 2 c clock signals, and p1.1 and p1.3 are the i 2 c data signals. for instance, to configure i2c0 pins (scl0, sda0), bit 0 and bit 4 of the gp1con register must be set to 1 to enable i 2 c mode. on the oth er hand, to configure i2c1 pins (scl1, sda1), bit 8 and bit 12 of the gp1con register must be set to 1 to enable i 2 c mode, as shown in the general - purpose input/output section. serial clock generation the i 2 c mast er in the system generates the serial clock for a transfer. the master channel can be configured to operate in fast mode (400 khz) or standard mode (100 khz). the bit rate is defined in the i2cxdiv mmr as follows: ) (2 ) 2 ( divl divh + + + = uclk clock serial f f here f uclk is th e clock before the clock divider. divh is the high period of the clock. divl is the low period of the clock. therefore, for 100 khz operation, divh = divl = 0xcf and for 400 khz divh = 0x28, divl = 0x3c the i2cxdiv register corresponds to divh:divl. i 2 c b us addresses slave mode in slave mode, the i2cxid0, i2cxid1, i2cxid2, and i2cxid3 registers contain the device ids. the device compares the four i2cxidx registers to the address byte received from the bus master. to be correctly addressed, the seven msbs o f either id register must be identical to the seven msbs of the first received address byte. the lsb of the id registers (the transfer direction bit) is ignored in the process of address recognition. the aduc7124 / aduc7126 also support 10 - bit addressing mode. when bit 1 of i2cxscon (adr10en bit) is set to 1, one 10- bit address is supported in slave mode and is stored in the i2cxid0 and i2cxid1 registers. the 10 - bit address is derived as follows: i2cxid0[0] is the read/write bit and is not part of the i 2 c address. i2cxid0[7:1] = address bits[6:0]. i2cxid1[2:0] = address bits[9:7]. i2cxid1[7:3] must be set to 11110b. rev. d | page 72 o f 110
data sheet aduc7124/aduc7126 maste r mode in master mode, the i2cxadr0 register is programmed with the i 2 c address of the device. in 7 - bit address mode, i2cxadr0[7:1] are set to the device address. i2cxadr0[0] is the read/write bit. in 10 - bit address mode, the 10 - bit address is created as follows: i2cxadr0[7:3] must be set to 11110b. i2cxadr0[2:1] = address bits[9:8]. i2cxadr1[7:0] = address bits[7:0]. i2cxadr0[0] is the read/write bit. i 2 c registers the i 2 c peripheral interfaces consists of a number of mmrs. these are described in the i 2 c master registers section. i 2 c master registers i 2 c master control register name: i2c0mcon, i2c1mcon address: 0xffff0800, 0xffff0900 default value : 0x0000, 0x0000 access: read/write function: this 16 - bit mmr con figures the i 2 c peripheral in master mode. table 102 . i2cxmcon mmr bit descriptions bit name description [15:9] reserved. these bits are reserved and should not be written to. 8 i2cmceni i 2 c transmission complete interrupt enable bit. set this bit to enable an interrupt on detecting a stop condition on the i 2 c bus. clear this bit to clear the interrupt source. 7 i2cnackeni i 2 c no acknowledge (nack) received interrupt enable bit. set this bit to enable interrupts w hen the i 2 c master receives a nack. clear this bit to clear the interrupt source. 6 i2caleni i 2 c arbitration lost interrupt enable bit. set this bit to enable interrupts when the i 2 c master is unable to gain control of the i 2 c bus. clear this bit to clear the interrupt source. 5 i2cmteni i 2 c transmit interrupt enable bit. set this bit to enable interrupts when the i 2 c master has transmitted a byte. clear this bit to clear the interrupt source. 4 i2cmreni i 2 c receive interrupt enable bit. set this bit to enable interrupts when the i 2 c master receives data. cleared by user to disable interrupts when the i 2 c master is receiving data. 3 reserved reserved. a value of 0 sh ould be written to this bit. 2 i2cilen i 2 c internal loopback enabl e. set this bit to enable loopback test mode. in this mode, the scl and sda signals are connected internally to their respective input signals. cleared by the user to disable loopback mode. 1 i2cbd i 2 c master backoff disable bit. set this bit to allow the device to compete for control of the bus even if another device is currently driving a start condition. clear this bit to wait until the i 2 c bus becomes free. 0 i2cmen i 2 c master enable bit. set by the user to enable i 2 c master mode. c lear this bit to disable i 2 c master mode. rev. d | page 73 of 110
aduc7124/aduc7126 data sheet i 2 c master status register name: i2c0msta, i2c1msta address: 0xffff0804, 0xffff0904 default value: 0x0000, 0x0000 access: read only function: this 16 - bit mmr is the i 2 c status register in master mode. tab le 103 . i2cxmsta mmr bit descriptions bit name description [15:11] reserved. 10 i2cbbusy i 2 c bus busy status bit. this bit is set to 1 when a start condition is detected on the i 2 c bus. this bit is cleared when a stop con dition is detected on the bus. 9 i2cmrxfo master rx fifo overflow. this bit is set to 1 when a byte is written to the rx fifo when it is already full. this bit is cleared in all other conditions. 8 i2cmtc i 2 c transmission complete status bit. t his bit is set to 1 when a transmission is complete between the master and the slave it was communicating with. if the i2cmceni bit in i2cxmcon is set, an interrupt is generated when this bit is set. clear this bit to clear the interrupt source. 7 i2cm na i 2 c master nack data bit. this bit is set to 1 when a nack condition is received by the master in response to a data write transfer. if the i2cnackeni bit in i2cxmcon is set, an interrupt is generated when this bit is set. this bit is cleared in a ll other conditions. 6 i2cmbusy i 2 c master busy status bit. set to 1 when the master is busy processing a transaction. cleared if the master is ready or if another master device has control of the bus. 5 i2cal i 2 c arbitration lost status bit. th is bit is set to 1 when the i 2 c master is unable to gain control of the i 2 c bus. if the i2caleni bit in i2cxmcon is set, an interrupt is generated when this bit is set. this bit is cleared in all other conditions. 4 i2cmna i 2 c master nack address bit . this bit is set to 1 when a nack condition is received by the master in response to an address. if the i2cnackeni bit in i2cxmcon is set, an interrupt is generated when this bit is set. this bit is cleared in all other conditions. 3 i2cmrxq i 2 c ma ster receive request bit. this bit is set to 1 when data enters the rx fifo. if the i2cmreni in i2cxmcon is set, an interrupt is generated. this bit is cleared in all other conditions. 2 i2cmtxq i 2 c master transmit request bit. this bit goes high if the tx fifo is empty or contains only one byte and the master has transmitted an address + write. if the i2cmteni bit in i2cxmcon is set, an interrupt is generated when this bit is set. this bit is cleared in all other conditions. [1:0] i2cmtfsta i 2 c master tx fifo status bits. 00 = i 2 c master tx fifo empty. 01 = one byte in master tx fifo. 10 = one byte in master tx fifo. 11 = i 2 c master tx fifo full. rev. d | page 74 o f 110
data sheet aduc7124/aduc7126 i 2 c master receive register name: i2c0mrx, i2c1mrx address: 0xffff0808, 0xffff090 8 default value : 0x00 access: read only function: this 8 - bit mmr is the i 2 c master receive register. i 2 c master transmit register name: i2c0mtx, i2c1mtx address: 0xffff080c 0xffff090c default value : 0x00, 0x00 access: read/write function: this 8 - bi t mmr is the i 2 c master transmit register. i 2 c master read count register name: i2c0mcnt0, i2c1mcnt0 address: 0xffff0810, 0xffff0910 default value : 0x0000, 0x0000 access: read/write function: this 16 - bit mmr holds the required number of bytes when the master begins a read sequence from a slave device. table 104 . i2cxmcnt0 mmr bit descriptions bit name description [15:9] reserved. 8 i2crecnt set this bit if more than 256 bytes are required from the slave. clear this bi t when reading 256 bytes or less. [7:0] i2crcnt these eight bits hold the number of bytes required during a slave read sequence, minus 1. if only a single byte is required, these bits should be set to 0. i 2 c master current read count register name: i2c 0mcnt1, i2c1mcnt1 address: 0xffff0814, 0xffff0914 default value : 0x00, 0x00 access: read only function: this 8 - bit mmr holds the number of bytes received so far during a read sequence with a slave device. i 2 c address 0 register name: i2c0adr0, i2c1adr 0 address: 0xffff0818, 0xffff0918 default value : 0x00 access: read/write function: this 8 - bit mmr holds the 7 - bit slave address + the read/write bit when the master begins communicating with a slave. table 105 . i2cxadr0 mmr i n 7 - bit address mode bit name description [7:1] i2cadr these bits contain the 7 - bit address of the required slave device. 0 r/w bit 0 is the read/write bit. when this bit = 1, a read sequence is requested. when this bit = 0, a write sequence is requested. table 106 . i2cxadr0 mmr in 10 - bit address mode bit name description [7:3] these bits must be set to [11110b] in 10 - bit address mode. [2:1] i2cmadr these bits contain addr[9:8] in 10 - bit addressing mode. 0 r/w read /write bit. when this bit = 1, a read sequence is requested. when this bit = 0, a write sequence is requested. rev. d | page 75 of 110
aduc7124/aduc7126 data sheet i 2 c address 1 register name: i2c0adr1, i2c1adr1 address: 0xffff081c, 0xffff091c default value : 0x00 access: read/write function: thi s 8 - bit mmr is used in 10 - bit addressing mode only. this register contains the least significant byte of the address. table 107 . i2cxadr1 mmr in 10 - bit address mode bit name description [7:0] i2cladr these bits contain addr[7: 0] in 10 - bit addressing mode. i 2 c master clock control register name: i2c0div, i2c1div address: 0xffff0824, 0xffff0924 default value : 0x1f1f access: read/write function: this mmr controls the frequency of the i 2 c clock generated by the master on to th e scl pin. for further details, see the i 2 c section. table 108 . i2cxdiv mmr bit name description [15:8] divh these bits control the duration of the high period of scl. [7:0] div l these bits control the duration of the low period of scl. i 2 c slave registers i 2 c slave control register name: i2c0scon, i2c1scon address: 0xffff0828, 0xffff0928 default value : 0x0000 access: read/write function: this 16 - bit mmr configures the i 2 c p eripheral in slave mode. table 109 . i2cxscon mmr bit descriptions bit name description [15:11] reserved. 10 i2cstxeni slave transmit interrupt enable bit. set this bit to enable an interrupt after a slave transmits a byte . clear this interrupt source. 9 i2csrxeni slave receive interrupt enable bit. set this bit to enable an interrupt after the slave receives data. clear this interrupt source. 8 i2csseni i 2 c stop condition detected interrupt enable bit. set th is bit to enable an interrupt on detecting a stop condition on the i 2 c bus. clear this interrupt source. 7 i2cnacken i 2 c nack enable bit. set this bit to nack the next byte in the transmission sequence. clear this bit to let the hardware control the ack/nack sequence. 6 reserved reserved. a value of 0 should be written to this bit. 5 i2cseten i 2 c early transmit interrupt enable bit. setting this bit enables a transmit request interrupt just after the positive edge of scl during the read bit transmission. clear this bit to enable a transmit request interrupt just after the negative edge of scl during the read bit transmission. 4 i2cgcclr i 2 c general call status and id clear bit. writing a 1 to this bit clears the general call status (i 2cgc) and id (i2cgcid[1:0]) bits in the i2cxssta register. clear this bit at all other times. rev. d | page 76 o f 110
data sheet aduc7124/aduc7126 bit name description 3 i2chgcen i 2 c hardware general call enable. when this bit and bit 2 are set, and having received a general call (address 0x00) and a data byte, the device c hecks the contents of the i2cxalt against the receive register. if the contents match, the device has received a hardware general call. this is used if a device needs urgent attention from a master device without knowing which master it needs to turn to. t his is a broadcast message to all master devices on the bus. the aduc7124 / aduc7126 watch for these addresses. the d evice that requires attention embeds its own address into the message. all masters listen, and the one that can handle the device contacts its slave and acts appropriately. the lsb of the i2cxalt register should always be written to 1, as per the i 2 c janua ry 2000 bus specification . set this bit and i2cgcen to enable hardware general call recognition in slave mode. clear this bit to disable recognition of hardware general call commands. 2 i2cgcen i 2 c general call enable. set this bit to enable the sl ave device to acknowledge an i 2 c general call, address 0x00 (write). the device then recognizes a data bit. if it receives a 0x06 (reset and write programmable part of the slave address by hard - ware) as the data byte, the i 2 c interface resets as per the i 2 c january 2000 bus specification. this command can be used to reset an entire i 2 c system. if it receives a 0x04 (write programmable part of the slave address by hardware) as the data byte, the general call interrupt status bit sets on any general call. th e user must take corrective action by reprogramming the device address. set this bit to allow the slave ack i 2 c general call commands. clear this bit to disable recognition of general call commands. 1 adr10en i 2 c 10 - bit address mode. set to 1 to enable 10 - bit address mode. clear to 0 to enable normal address mode. 0 i2csen i 2 c slave enable bit. set by the user to enable i 2 c slave mode. clear this bit to disable i 2 c slave mode. i 2 c slave status registers name: i2c0ssta, i2c1ssta addre ss: 0xffff082c, 0xffff092c default value : 0x0000, 0x0000 access: read only function: this 16 - bit mmr is the i 2 c status register in slave mode. table 110 . i2cxssta mmr bit descriptions bit name description 15 reserved. 14 i 2csta this bit is set to 1 if a start condition followed by a matching address is detected, a start byte (0x01) is received, or general calls are enabled and a general call code of (0x00) is received. this bit is cleared on receiving a stop condition. 13 i2creps this bit is set to 1 if a repeated start condition is detected. this bit is cleared on receiving a stop condition. a read of the i2cxssta register also clears this bit. [12:11] i2cid[1:0] i 2 c address matching register. these bits indicate w hich i2cxidx register matches the received address. [00] = received address matches i2cxid0. [01] = received address matches i2cxid1. [10] = received address matches i2cxid2. [11] = received address matches i2cxid3. 10 i2css i 2 c stop condition after start detected bit. this bit is set to 1 when a stop condition is detected after a previous start and matching address. when the i2csseni bit in i2cxscon is set, an interrupt is generated. this bit is cleared by reading this register. rev. d | page 77 of 110
aduc7124/aduc7126 data sheet bit name description [9:8] i2cgcid[1:0] i 2 c general call id bits. [00] = no general call received. [01] = general call reset and program address. [10] = general program address. [11] = general call matching alternative id. note that these bits are not cleared by a general call reset command. clear these bits by writing a 1 to the i2cgcclr bit in i2cxscon . 7 i2cgc i 2 c general call status bit. this bit is set to 1 if the slave receives a general call command of any type. if the command received is a reset command, then all registers retur n to their default states. if the command received is a hardware general call, the rx fifo holds the second byte of the command and this can be compared with the i2cxalt register. clear this bit by writing a 1 to the i2cgcclr bit in i2cxscon . 6 i2csbus y i 2 c slave busy status bit. set to 1 when the slave receives a start condition. cleared by hardware if the received address does not match any of the i2cxidx registers, the slave device receives a stop condition, or a repeated start address does not match any of the i2cxidx registers. 5 i2csna i 2 c slave nack data bit. this bit is set to 1 when the slave responds to a bus address with a nack. this bit is asserted if a nack was returned because there was no data in the tx fifo or the i2cnacken bit was set in the i2cxscon register. this bit is cleared in all other conditions. 4 i2csrxfo slave rx fifo overflow. this bit is set to 1 when a byte is written to the rx fifo when it is already full. this bit is cleared in all other conditions. 3 i2csrxq i 2 c slave receive request bit. this bit is set to 1 when the slave rx fifo is not empty. this bit causes an interrupt to occur when the i2csrxeni bit in i2cxscon is set. the rx fifo must be read or flushed to clear this bit. 2 i2cstxq i 2 c slave transmit request bit. this bit is set to 1 when the slave receives a matching address followed by a read. if the i2cseten bit in i2cxscon = 0, this bit goes high just after the negative edge of scl during the read bit transmission. if the i2cset en bit in i2cxscon = 1, this bit goes high just after the positive edge of scl during the read bit transmission. this bit causes an interrupt to occur when the i2cstxeni bit in i2cxscon is set. this bit is cleared in all other conditions. 1 i2cstfe i 2 c slave fifo underflow status bit. this bit goes high if the tx fifo is empty when a master requests data from the slave. this bit is asserted at the rising edge of scl during the read bit. this bit is cleared in all other conditions. 0 i2cetsta i 2 c slave early transmit fifo status bit. if the i2cseten bit in i2cxscon = 0, this bit goes high if the slave tx fifo is empty. if the i2cseten bit in i2cxscon = 1, this bit goes high just after the positive edge of scl during the write bit transmission. this bit asserts once only for a transfer. this bit is cleared after being read. rev. d | page 78 o f 110
data sheet aduc7124/aduc7126 i 2 c slave receive registers name: i2c0srx, i2c1srx address: 0xffff0830, 0xffff0930 default value : 0x00 access: read function: this 8 - bit mmr is the i 2 c slave recei ve register. i 2 c slave transmit registers name: i2c0stx, i2c1stx address: 0xffff0834, 0xffff0934 default value : 0x00 access: write function: this 8 - bit mmr is the i 2 c slave transmit register. i 2 c hardware general call recognition registers name: i2c0 alt, i2c1alt address: 0xffff0838, 0xffff0938 default value : 0x00 access: read/write function: this 8 - bit mmr is used with hardware general calls when i2cxscon bit 3 is set to 1. this register is used in cases where a master is unable to generate an add ress for a slave, and instead, the slave must generate the address for the master. i 2 c slave device id registers name: i2c0idx, i2c1idx addresses: 0xffff093c = i2c1id0 0xffff083c = i2c0id0 0xffff0940 = i2c1id1 0xffff0840 = i2c0id1 0xffff0944 = i2c1i d2 0xffff0844 = i2c0id2 0xffff0948 = i2c1id3 0xffff0848 = i2c0id3 default value : 0x00 access: read/write function: these 8 - bit mmrs are programmed with i 2 c bus ids of the slave. see the i2c bus addresses sec tion for further details. i 2 c common registers i 2 c fifo status register name: i2c0fsta, i2c1fsta address: 0xffff084c, 0xffff094c default value : 0x0000 access: read/write function: these 16 - bit mmrs contain the status of the rx/tx fifos in both master and slave modes. table 111 . i2cxfsta mmr bit descriptions bit name description [15:10] reserved. 9 i2cfmtx set this bit to 1 to flush the master tx fifo. 8 i2cfstx set this bit to 1 to flush the slave tx fifo. [7:6] i2cmrx sta i 2 c master receive fifo status bits. [00] = fifo empty. [01] = byte written to fifo. [10] = one byte in fifo. [11] = fifo full. [5:4] i2cmt xsta i 2 c master transmit fifo status bits. [00] = fifo empty. [01] = byte written to fifo. [10] = one byte in fifo. [11] = fifo full. [3:2] i2csrxsta i 2 c slave receive fifo status bits. [00] = fifo empty. [01] = byte written to fifo. [10] = one byte in fifo. [11] = fifo full. [1:0] i2cstxsta i 2 c slave transmit fifo status bits. [00] = fifo empty. [01] = byte written to fifo. [10] = one byte in fifo. [11] = fifo full. rev. d | page 79 of 110
aduc7124/aduc7126 data sheet rev. d | page 80 of 110 pwm general overview the aduc7124 / aduc7126 integrate a 6-channel pwm interface (pwm0 to pwm5). the pwm outputs can be configured to drive an h-bridge or can be used as standard pwm outputs. on power-up, the pwm outputs default to h-bridge mode. this ensures that the motor is turned off by default. in standard pwm mode, the outputs are arranged as three pairs of pwm pins. the user has control over the period of each pair of outputs and over the duty cycle of each individual output. table 112. pwm mmrs name function pwmcon0 pwm control. pwm0com0 compare register 0 for pwm output 0 and pwm output 1. pwm0com1 compare register 1 for pwm output 0 and pwm output 1. pwm0com2 compare register 2 for pwm output 0 and pwm output 1. pwm0len frequency control for pwm output 0 and pwm output 1. pwm1com0 compare register 0 for pwm output 2 and pwm output 3. pwm1com1 compare register 1 for pwm output 2 and pwm output 3. pwm1com2 compare register 2 for pwm output 2 and pwm output 3. pwm1len frequency control for pwm output 2 and pwm output 3. pwm2com0 compare register 0 for pwm output 4 and output 5 pwm2com1 compare register 1 for pwm output 4 and output 5 pwm2com2 compare register 2 for pwm output 4 and output 5 pwm2len frequency control for pwm output 4 and pwm output 5. pwmcon1 pwm control register pwmclri pwm interrupt clear. in all modes, the pwmxcomx mmrs control the point at which the pwm outputs change state. an example of the first pair of pwm outputs (pwm0 and pwm1) is shown in figure 49. high side (pwm0) low side (pwm1) pwm0com2 pwm0com1 pwm0com0 pwm0len 0 9123-120 figure 49. pwm timing the pwm clock is selectable via pwmcon with one of the following values: uclk divided by 2, 4, 8, 16, 32, 64, 128, or 256. the length of a pwm period is defined by pwmxlen. the pwm waveforms are set by the count value of the 16-bit timer and the compare registers contents, as shown with the pwm0 and pwm1 waveforms in figure 49. the low-side waveform, pwm1, goes high when the timer count reaches pwm0len, and it goes low when the timer count reaches the value held in pwm0com2 or when the high-side waveform (pwm0) goes low. the high-side waveform, pwm0, goes high when the timer count reaches the value held in pwm0com0, and it goes low when the timer count reaches the value held in pwm0com1.
data sheet aduc7124/aduc7126 table 113 . pwmcon0 mmr bit descriptions bit name description 14 sync enables pwm synchronization. set to 1 by the user so that all pwm counters are reset on the next clock edge after the detection of a high - to - low transition on the p3.7/pwm sync pin. cleared by the user to ignore transitions on the p3.7/pwm sync pin. 13 pwm5inv set to 1 by the user to invert pwm5. cleared by the user to use pwm5 in normal mode. 12 pwm3inv set to 1 by the user to invert pwm3. cleared by the user to use pwm3 in normal mode. 11 pwm1inv set to 1 by the user to invert pwm1. cleared by the user to use pwm1 in normal mode. 10 pwmtrip set to 1 by the user to enable pwm trip interrupt. when the pwm trip input (pin p3.6/pwm trip or pin p0.4/pwm trip ) is low, the pwmen bit is cleared and an interrupt is generated. cleared by the user to disable the pwmtrip interrupt. 9 ena if hoff = 0 and hmode = 1; no te that, if not in h - bridge mode, this bit has no effect. set to 1 by the user to enable pwm outputs. cleared by the user to disable pwm outputs. if hoff = 1 and hmode = 1, see table 114. [8:6] pwmcp[2:0] pwm clock prescaler bits. sets the uclk divider. [000] = uclk/2. [001] = uclk/4. [010] = uclk/8. [011] = uclk/16. [100] = uclk/32. [101] = uclk/64. [110] = uclk/128. [111] = uclk/256. 5 poinv set to 1 by the user to invert all pw m outputs. cleared by the user to use pwm outputs as normal. 4 hoff high side off. set to 1 by the user to force pwm0 and pwm2 outputs high. this also forces pwm1 and pwm3 low. cleared by the user to use the pwm outputs as normal. 3 lcomp loa d compare registers. set to 1 by the user to load the internal compare registers with the values in pwmxcomx on the next transition of the pwm timer from 0x00 to 0x01. cleared by the user to use the values previously stored in the internal compare r egisters. 2 dir direction control. set to 1 by the user to enable pwm0 and pwm1 as the output signals while pwm2 and pwm3 are held low. cleared by the user to enable pwm2 and pwm3 as the output signals while pwm0 and pwm1 are held low. 1 hmode ena bles h - bridge mode. 1 set to 1 by the user to enable h - bridge mode and bit 1 to bit 5 of pwmcon. cleared by the user to operate the pwms in standard mode. 0 pwmen set to 1 by the user to enable all pwm outputs. cleared by the user to disable all pwm outputs. 1 in h - bridge mode, hmode = 1. see table 114 to determine the pwm outputs. rev. d | page 81 of 110
aduc7124/aduc7126 data sheet table 114 . pwm output selection, hmode = 1 pwmcon0 mmr 1 pwm outputs 2 ena hoff poinv dir pwm0 pwm1 pwm2 pwm3 0 0 x x 1 1 1 1 x 1 x x 1 0 1 0 1 0 0 0 0 0 hs ls 1 0 0 1 hs ls 0 0 1 0 1 0 hs ls 1 1 1 0 1 1 1 1 h s ls 1 x = dont care. 2 hs = high side, ls = low side. on power - up, pwmcon0 defaults to 0x12 (hoff = 1 and hmode = 1). all gpio pins associated with the pwm are configured in pwm mode by default (see table 115). table 115 . compare registers name address default value access pwm0com0 0xffff0f84 0x0000 r/w pwm0com1 0xffff0f88 0x0000 r/w pwm0com2 0xffff0f8c 0x0000 r/w pwm1com0 0xffff0f94 0x0000 r/w pwm1com1 0xffff0f98 0x0000 r/w pw m1com2 0xffff0f9c 0x0000 r/w pwm2com0 0xffff0fa4 0x0000 r/w pwm2com1 0xffff0fa8 0x0000 r/w pwm2com2 0xffff0fac 0x0000 r/w the pwm trip interrupt can be cleared by writing any value to the pwmclri mmr. note that, when using the pwm trip interrupt, users should make sure that the pwm interrupt has been cleared before exiting the isr. this prevents generation of multiple interrupts. pwm convert start control the pwm can be configured to generate an adc convert start signal after the active low side signal goes high. there is a program mable delay between the time that the low - side signal goes high and the convert start signal is generated. this is controlled via the pwmcon1 mmr. if the delay selected is higher than the width of the pwm pulse, the interrupt remains low. table 116 . pwmcon1 mmr bit descriptions ( address = 0xffff0fb4; default value = 0x00) bit value name description 7 csen set to 1 by the user to enable the pwm to generate a convert start signal. cleared by user to d isable the pwm convert start signal. [3:0] csd3 convert start delay. delays the convert start signal by a number of clock pulses. csd2 csd1 csd0 0000 four clock pulses. 0001 eight clock pulses. 0010 12 clock pulses. 0011 16 clock pulses. 0100 20 clock pulses. 0101 24 clock pulses. 0110 28 clock pulses. 0111 32 clock pulses. 1000 36 clock pulses. 1001 40 clock pulses. 1010 44 clock pulses. 1011 48 clock pulses. 1100 52 clock pulses. 1101 56 clock pulses . 1110 60 clock pulses. 1111 64 clock pulses. when calculating the time from the convert start delay to the start of an adc conversion, the user must take account of internal delays. the following example shows the case of a delay of four clocks. on e additional clock is required to pass the convert start signal to the adc logic. once the adc logic receives the convert start signal, an adc conversion begins on the next adc clock edge (see figure 50). uclk low side count pwm signal signal passed to adc logic to convst 09123-045 figur e 50 . adc conversion rev. d | page 82 o f 110
data sheet aduc7124/aduc7126 rev. d | page 83 of 110 programmable logic array (pla) every aduc7124/ aduc7126 integrates a fully programmable logic array (pla) that consists of two independent but interconnected pla blocks. each block consists of eight pla elements, giving each part a total of 16 pla elements. each pla element contains a two-input look up table that can be configured to generate any logic output function based on two inputs and a flip-flop. this is represented in figure 51. 09123-133 4 2 0 1 3 a b look-up table figure 51. pla element in total, 40 gpio pins are available on the aduc7124 / aduc7126 for the pla. these include 16 input pins and 16 output pins that must be configured in the gpxcon register as pla pins before using the pla. note that the comparator output is also included as one of the 16 input pins. the pla is configured via a set of user mmrs. the output(s) of the pla can be routed to the internal interrupt system, to the conv start signal of the adc, to an mmr, or to any of the 16 pla output pins. the two blocks can be interconnected as follows: ? output of element 15 (block 1) can be fed back to input 0 of mux 0 of element 0 (block 0). ? output of element 7 (block 0) can be fed back to input 0 of mux 0 of element 8 (block 1). table 117. element input/output 1 pla block 0 pla block 1 element input output element input output 0 p1.0 p1.7 8 p3.0 p4.0 1 p1.1 p0.4 9 p3.1 p4.1 2 p1.2 p0.5 10 p3.2 p4.2 3 p1.3 p0.6 11 p3.3 p4.3 4 p1.4 p0.7 12 p3.4 p4.4 5 p1.5 p2.0 13 p3.5 p4.5 6 p1.6 p2.1 14 p3.6 p4.6 7 p0.0 p2.2 15 p3.7 p4.7 1 not all pins in this table are connected to external pins. however, they may be routed internally via the pla. see table 122 for further details. pla mmrs interface the pla peripheral interface consists of the 22 mmrs. table 118. plaelmx registers name address default value access plaelm0 0xffff0b00 0x0000 r/w plaelm1 0xffff0b04 0x0000 r/w plaelm2 0xffff0b08 0x0000 r/w plaelm3 0xffff0b0c 0x0000 r/w plaelm4 0xffff0b10 0x0000 r/w plaelm5 0xffff0b14 0x0000 r/w plaelm6 0xffff0b18 0x0000 r/w plaelm7 0xffff0b1c 0x0000 r/w plaelm8 0xffff0b20 0x0000 r/w plaelm9 0xffff0b24 0x0000 r/w plaelm10 0xffff0b28 0x0000 r/w plaelm11 0xffff0b2 c 0x0000 r/w plaelm12 0xffff0b30 0x0000 r/w plaelm13 0xffff0b34 0x0000 r/w plaelm14 0xffff0b38 0x0000 r/w plaelm15 0xffff0b3 c 0x0000 r/w the plaelmx are element 0 to element 15 control registers. they configure the input and output mux of each element, select the function in the look up table, and bypass/use the flip- flop (see table 119 and table 122). table 119. plaelmx mmr bit descriptions bit value description [31:11] reserved. [10:9] mux 0 control (see table 122). [8:7] mux 1 control (see table 122). 6 mux 2 control. set by the user to select the output of mux 0. cleared by the user to select the bit value from pladin. 5 mux 3 control. set by the user to select the input pin of the particular element. cleared by the user to select the output of mux 1. [4:1] look-up table control. 0000 0. 0001 nor. 0010 b and not a. 0011 not a. 0100 a and not b. 0101 not b. 0110 exor. 0111 nand. 1000 and. 1001 exnor. 1010 b. 1011 not a or b. 1100 a. 1101 a or not b. 1110 or. 1111 1. 0 mux 4 control. set by the user to bypass the flip-flop. cleared by the user to select the flip-flop (cleared by default).
aduc7124/aduc7126 data sheet placlk register name: placlk address: 0xffff0b40 default value: 0x00 access: read/write placlk is the clock selection for the flip - flops of block 0 and block 1. note that the ma ximum frequency when using the gpio pins as the clock input for the pla blocks is 41.78 mhz. table 120 . placlk mmr bit descriptions bit value description 7 reserved. [6:4] block 1 clock source selection. 000 gpio clock on p0.5. 001 gpio clock on p0.0. 010 gpio clock on p0.7. 011 hclk. 100 oclk (32.768 khz). 101 timer1 overflow. 110 uclk. 111 internal 32,768 oscillator. 3 reserved. [2:0] block 0 clock source selection. 000 gpio clock on p0.5. 001 gpio clock on p0.0. 010 gpio clock on p0.7. 011 hclk. 100 oclk (32.768 khz). 101 timer1 overflow. other reserved. plairq register name: plairq address: 0xffff0b44 default value : 0x00000000 access: read/write plairq enables irq0 and/or irq1 and selects the source of the irq. table 121 . plairq mmr bit descriptions bit value description [15:13] reserved. 12 pla irq1 enable bit. set by the user to ena ble irq1 output from pla . cleared by the user to disable irq1 output from pla. [11:8] pla irq1 source. 0000 pla element 0. 0001 pla element 1. 1111 pla element 15. [7:5] reserved. 4 pla irq0 enable bit. set by the user to enable irq0 output from pla . cleared by the user to disable irq0 output from pla. [3:0] pla irq0 source. 0000 pla element 0. 0001 pla element 1. 1111 pla element 15. table 122 . feedback configuration bit value plaelm0 plaelm1 to plaelm7 pl aelm8 plaelm9 to plaelm15 [10:9] 00 element 15 element 0 element 7 element 8 01 element 2 element 2 element 10 element 10 10 element 4 element 4 element 12 element 12 11 element 6 element 6 element 14 element 14 [8:7] 00 element 1 element 1 element 9 element 9 01 element 3 element 3 element 11 element 11 10 element 5 element 5 element 13 element 13 11 element 7 element 7 element 15 element 15 rev. d | page 84 o f 110
data sheet aduc7124/aduc7126 plaadc register name: plaadc address: 0xffff0b48 default value: 0x00000000 access: read/write p laadc is the pla source for the adc start conversion signal. table 123 . plaadc mmr bit descriptions bit value description [31:5] reserved. 4 adc start conversion enable bit. set by the user to enable adc start conversion fro m pla . cleared by the user to disable adc start conversion from pla. [3:0] adc start conversion source. 0000 pla element 0. 0001 pla element 1. 1111 pla element 15. pladin register name: pladin address: 0xffff0b4c default value: 0x00000000 ac cess: read/write pladin is a data input mmr for pla. table 124 . pladin mmr bit descriptions bit description [31:16] reserved. [15:0] input bit to element 15 to element 0. pladout register name: pladout address: 0xffff0b50 def ault value: 0x00000000 access: read only pladout is a data output mmr for pla. this register is always updated. table 125 . pladout mmr bit descriptions bit description [31:16] reserved. [15:0] output bit from element 15 to eleme nt 0. plalck register name: plalck address: 0xffff0b54 default value: 0x00 access: write only plalck is a pla lock option. bit 0 is written only once. when set, it does not allow modification of any of the pla mmrs, except pladin. a pla tool is provi ded in the development system to easily configure the pla. rev. d | page 85 of 110
aduc7124/aduc7126 data sheet processor reference peripherals interrupt system there are 25 interrupt sources on the aduc7124 / aduc7126 that are controlled by the interrupt controller. all interrupts are generated from the on - chip peripherals, except for the software interrupt (swi), which is programmable by the user. the arm7tdmi cpu cor e recognizes interrupts as one of two types: a normal interrupt request (irq) and a fast interrupt request (fiq). all the interrupts can be masked separately. the control and configuration of the interrupt system is managed through a number of interrupt - r elated registers. the bits in each irq and fiq register represent the same interrupt source as described in table 126 . the aduc7124 / aduc7126 contain a vectored interrupt control - ler (vic) that supports nested interrupts up to eight levels. the vic also allows the programmer to assign priority levels to all interrupt sources. i nterrupt nesting must be enabled by setting the enirqn bit in the irqconn register. a number of extra mmrs are used when the full - vectored interrupt controller is enabled. irqsta/fiqsta should be saved immediately upon entering the interrupt service routi ne (isr) to ensure that all valid interrupt sources are serviced. table 126 . irq/fiq mmrs bit descriptions bit description comments 0 all interrupts ored (fiq only) this bit is set if any fiq is active. 1 software interrupt user programmable interrupt source. 2 timer0 general - purpose timer 0. 3 timer1 general - purpose timer 1. 4 timer2 or wake - up timer general - purpose timer 2 or wake - up timer. 5 timer3 or watchdog timer general - purpose timer 3 or watchdog timer. 6 flash contro l 0 flash controller for block 0 interrupt. 7 flash control 1 flash controller for block 1 interrupt. 8 adc adc interrupt source bit. 9 uart 0 uart 0 interrupt source bit. 10 uart 1 uart 1 interrupt source bit. 11 pll lock pll lock bit. 12 i2c0 master ir q i 2 c master interrupt source bit. 13 i2c0 slave irq i 2 c slave interrupt source bit. 14 i2c1 master irq i 2 c master interrupt source bit. 15 i2c1 slave irq i 2 c slave interrupt source bit. 16 spi spi interrupt source bit. 17 xirq0 (gpio irq0 ) external interrupt 0. 18 comparator voltage comparator source bit. 19 psm power supply monitor. 20 xirq1 (gpio irq1) external interrupt 1. bit description comments 21 pla irq0 pla block 0 irq bit. 22 xirq2 (gpio irq2 ) external interrupt 2. 23 xirq3 (gpio irq3) external interrupt 3. 24 pla irq1 pla block 1 irq bit. 25 pwm pwm trip interrupt source bit. irq the irq is the exception signal to enter the irq mode of the processor. it services general - purpose interrupt handling of internal and external events. all 32 bits are logica lly ored to create a single irq signal to the arm7tdmi core. descriptions of the four 32 - bit registers dedicated to irq follow. irqsta register irqsta is a read - only register that provides the current - enabled irq source status (effectively a logic and of the irqsig and irqen bits). when set to 1, that source generates an active irq request to the arm7tdmi core. there is no priority encoder or interrupt vector generation. this function is implemented in software in a common interrupt handler routine. irqsta register name: irqsta address: 0xffff0000 default value: 0x00000000 access: read only irqsig register irqsig reflects the status of the various irq sources. if a periph - eral generates an irq signal, the corresponding bit in the irqsig is set; otherwi se, it is cleared. the irqsig bits clear when the interrupt in the particular peripheral is cleared. all irq sources can be masked in the irqen mmr. irqsig is read only. this register should not be used in an interrupt service routine for determining the s ource of an irq exception; irqsta should only be used for this purpose. irqsig register name: irqsig address: 0xffff0004 default value : 0x00000000 access: read only rev. d | page 86 o f 110
data sheet aduc7124/aduc7126 irqen register irqen provides the value of the current enable mask. when a bit is set to 1, the corresponding source request is enabled to create an irq exception. when a bit is set to 0, the correspond - ing source request is disabled or masked, which does not create an irq exception. the irqen register cannot be used to disable an interrup t. irqen register name: irqen address: 0xffff0008 default value : 0x00000000 access: read/write irqclr register irqclr is a write - only register that allows the irqen register to clear to mask an interrupt source. each bit that is set to 1 clears the cor responding bit in the irqen register without affecting the remaining bits. the pair of registers, irqen and irqclr, allow independent manipulation of the enable mask without requiring an atomic read - modify - write. this register should be used to disable an interrupt source only during the following conditions: ? in the interrupt sources interrupt service routine. ? when the peripheral is temporarily disabled by its own control register. this register should not be used to disable an irq source if that irq sourc e has an interrupt pending or may have an interrupt pending. irqclr register name: irqclr address: 0xffff000c default value : 0x00000000 access: write only fast interrupt reque st (fiq) the fast interrupt request (fiq) is the exception signal to enter th e fiq mode of the processor. it is provided to service data transfer or communication channel tasks with low latency. the fiq interface is identical to the irq interface and provides the second level interrupt (highest priority). four 32 - bit registers are dedicated to fiq: fiqsig, fiqen, fiqclr, and fiqsta. bit 31 to bit 1 of fiqsta are logically ored to create the fiq signal to the core and to bit 0 of both the fiq and irq registers (fiq source). the logic for fiqen and fiqclr does not allow an interrupt source to be enabled in both irq and fiq masks. a bit set to 1 in fiqen clears, as a side effect, the same bit in irqen. likewise, a bit set to 1 in irqen clears, as a side effect, the same bit in fiqen. an interrupt source can be disabled in both the irqe n and fiqen masks. fiqsig fiqsig reflects the status of the different fiq sources. if a peripheral generates an fiq signal, the corresponding bit in the fiqsig is set; otherwise, it is cleared. the fiqsig bits are cleared when the interrupt in the particu lar peripheral is cleared. all fiq sources can be masked in the fiqen mmr. fiqsig is read only. fiqsig register name: fiqsig address: 0xffff0104 default value: 0x00000000 access: read only fiqen fiqen provides the value of the current enable mask. whe n a bit is set to 1, the corresponding source request is enabled to create an fiq exception. when a bit is set to 0, the correspond - ing source request is disabled or masked, which does not create an fiq exception. the fiqen register cannot be used to disab le an interrupt . fiqen register name: fiqen address: 0xffff0108 default value : 0x00000000 access: read/write fiqclr fiqclr is a write - only register that allows the fiqen register to clear to mask an interrupt source. each bit that is set to 1 clears th e corresponding bit in the fiqen register without affecting the remaining bits. the pair of registers, fiqen and fiqclr, allows independent manipulation of the enable mask without requiring an atomic read - modify - write. this register should be used to disab le an interrupt source only during the following conditions: ? in the interrupt sources interrupt service routine. ? the peripheral is temporarily disabled by its own control register. this register should not be used to disable an irq source if that irq sourc e has an interrupt pending or may have an interrupt pending. rev. d | page 87 of 110
aduc7124/aduc7126 data sheet rev. d | page 88 of 110 fiqclr register name: fiqclr address: 0xffff010c default value: 0x00000000 access: write only fiqsta fiqsta is a read-only register that provides the current enabled fiq source status (effectively a logic and of the fiqsig and fiqen bits). when set to 1, that source generates an active fiq request to the arm7tdmi core. there is no priority encoder or interrupt vector generation. this function is implemented in software in a common interrupt handler routine. fiqsta register name: fiqsta address: 0xffff0100 default value: 0x00000000 access: read only programmed interrupts because the programmed interrupts are not maskable, they are controlled by another register (swicfg) that writes into the irqsta and irqsig registers a nd/or the fiqsta and fiqsig registers at the same time. the 32-bit register dedicated to software interrupt is swicfg (described in table 127). this mmr allows control of a pro- grammed source interrupt. table 127. swicfg mmr bit descriptions bit description [31:3] reserved. 2 programmed interrupt fiq. setting/clearing this bit corresponds to setting/clearing bit 1 of fiqsta and fiqsig. 1 programmed interrupt irq. se tting/clearing this bit corresponds to setting/clearing bit 1 of irqsta and irqsig. 0 reserved. any interrupt signal must be active for at least the minimum interrupt latency time to be detected by the interrupt controller and to be detected by the user in the irqsta/fiqsta register. internal arbiter logic bits[31:23] unused bits[22:7] (irqbase) bits[6:2] highest priority active irq bits[1:0] lsbs irq_source pointer function (irqvec) fiq_source interrupt vector programmable priority per interrut (irqp0/irqp1/irqp2/irqp3) 09123-054 figure 52. interrupt structure vectored interrupt controller (vic) the aduc7124 / aduc7126 incorporate an enhanced interrupt control system or (vectored interrupt controller). the vectored interrupt controller for irq interrupt sources is enabled by set- ting bit 0 of the irqconn register. similarly, bit 1 of irqconn enables the vectored interrupt controller for the fiq interrupt sources. the vectored interrupt controller provides the following enhancements to the standard irq/fiq interrupts: ? vectored interruptsallows a user to define separate interrupt service routine addresses for every interrupt source. this is achieved by using the irqbase and irqvec registers. ? irq/fiq interruptscan be nested up to eight levels depending on the priority settings. an fiq still has a higher priority than an irq. therefore, if the vic is enabled for both the fiq and irq and prioritization is maximized, it is possible to have 16 separate interrupt levels. ? programmable interrupt prioritiesusing the irqp0 to irqp3 registers, an interrupt source can be assigned an interrupt priority level value between 0 and 7. vic mmrs irqbase register the vector base register, irqbase, is used to point to the start address of memory used to store 32 pointer addresses. these pointer addresses are the addresses of the individual interrupt service routines. name: irqbase address: 0xffff0014 default value: 0x00000000 access: read/write table 128. irqbase mmr bit descriptions bit type initial value description [31:16] read only reserved always read as 0. [15:0] r/w 0 vector base address.
data sheet aduc7124/aduc7126 irqvec register the irq interrupt vecto r register, irqvec points to a memory address containing a pointer to the interrupt service routine of the currently active irq. this register should only be read when an irq occurs and irq interrupt nesting has been enabled by setting bit 0 of the irqconn register. name: irqvec address: 0xffff001c default value : 0x00000000 access: read only table 129 . irqvec mmr bit descriptions bit type initial value description [31:23] r 0 always read as 0. [22:7] r/w 0 irqbase register v alue. [6:2] r 0 highest priority source. this is a value between 0 and 27 represent - ing the possible interrupt sources. for example, if the highest currently active irq is timer 2, then these bits are [00100]. [1:0] reser ved 0 reserved bits. priority re gisters the irq interrupt vector register, irqvec points to a memory address containing a pointer to the interrupt service routine of the currently active irq. this register should only be read when an irq occurs and irq interrupt nesting has been enabled by setting bit 0 of the irqconn register. irqp0 register name: irqp0 address: 0xffff0020 default value : 0x00000000 access: read/write table 130 . irqp0 mmr bit descriptions bit name description 31 reserved. [30:28] flash1pi a priority level of 0 to 7 can be set for the flash block 1 controller interrupt source. 27 reserved. [26:24] flash0pi a priority level of 0 to 7 can be set for the flash block 0 controller interrupt source. 23 reserved. [22:20] t3pi a priority level of 0 to 7 can be set for timer 3. 19 reserved. bit name description [18:16] t2pi a priority level of 0 to 7 can be set for timer2. 15 reserved. [14:12] t1pi a priority level of 0 to 7 can be set for timer1. 11 reserved. [10:8] t0pi a priority level of 0 to 7 can be s et for timer0. 7 reserved. [6:4] swintp a priority level of 0 to 7 can be set for the software interrupt source. [3:0] interrupt 0 cannot be prioritized. irqp1 register name: irqp1 address: 0xffff0024 default value : 0x00000000 access: read/write table 131 . irqp1 mmr bit descriptions bit name description 31 reserved. [30:28] i2c1spi a priority level of 0 to 7 can be set for the i2c1 slave. 27 reserved. [26:24] i2c1mpi a priority level of 0 to 7 can be set for the i2c 1 master. 23 reserved. [22:20] i2c0spi a priority level of 0 to 7 can be set for the i2c0 slave. 19 reserved. [18:16] i2c0mpi a priority level of 0 to 7 can be set for the i 2 c 0 master. 15 reserved. [14:12] pllpi a priority level of 0 to 7 can be set for the pll lock interrupt. 11 reserved. [10:8] uart1pi a priority level of 0 to 7 can be set for uart1. 7 reserved. [6:4] uart0pi a priority level of 0 to 7 can be set for uart0. 5 reserved. [2:0] adcpi a priority level of 0 to 7 can be set f or the adc interrupt source. rev. d | page 89 of 110
aduc7124/aduc7126 data sheet irqp2 register name: irqp2 address: 0xffff0028 default value : 0x00000000 access: read/write table 132 . irqp2 mmr bit descriptions bit name description 31 reserved. [30:28] irq3pi a priority l evel of 0 to 7 can be set for irq3. 27 reserved. [26:24] irq2pi a priority level of 0 to 7 can be set for irq2. 23 reserved. [22:20] pla0pi a priority level of 0 to 7 can be set for pla irq0. 19 reserved. [18:16] irq1pi a priority level of 0 to 7 can be set for irq1. 15 reserved. [14:12] psmpi a priority level of 0 to 7 can be set for the power supply monitor interrupt source. 11 reserved. [10:8] compi a priority level of 0 to 7 can be set for the comparator. 7 reserved. [6:4] irq0pi a p riority level of 0 to 7 can be set for irq0. 3 reserved. [2:0] spipi a priority level of 0 to 7 can be set for spi. irqp3 register name: irqp3 address: 0xffff002c default value : 0x00000000 access: read/write table 133 . irqp 3 mmr bit descriptions bit name description [31:7] reserved. [6:4] pwmpi a priority level of 0 to 7 can be set for pwm. 3 reserved. [2:0] pla1pi a priority level of 0 to 7 can be set for pla irq1. irqconn register the irqconn register is the irq an d fiq control register. it contains two active bits: the first to enable nesting and prioritiza - tion of irq interrupts and the other to enable nesting and prioritization of fiq interrupts. if these bits are cleared, fiqs and irqs can still be used, but it is not possible to nest irqs or fiqs, nor is it possible to set an interrupt source priority level. in this default state, an fiq does have a higher priority than an irq. name: irqconn address: 0xffff0030 default value : 0x00000000 access: read/write t able 134 . irqconn mmr bit descriptions bit name description 31:2 reserved. these bits are reserved and should not be written to. 1 enfiqn setting this bit to 1 enables nesting of fiq interrupts. clearing this bit means no nesti ng or prioritization of fiqs is allowed. 0 enirqn setting this bit to 1 enables nesting of irq interrupts. clearing this bit means no nesting or prioritization of irqs is allowed. irqstan register if irqconn bit 0 is asserted and irqvec is read, one of t he irqstan[7:0] bits is asserted. the bit that asserts depends on the priority of the irq. if the irq is of priority 0, then bit 0 asserts, if priority 1, then bit 1 asserts, and so on. when a bit is set in this register, all interrupts of that priority an d lower are blocked. to clear a bit in this register, all bits of a higher priority must be cleared first. it is only possible to clear one bit at a time. for example, if this register is set to 0x09, writing 0xff changes the register to 0x08, and writing 0xff a second time changes the register to 0x00. name: irqstan address: 0xffff003c default value : 0x00000000 access: read/write table 135 . irqstan mmr bit descriptions bit name description 31:8 reserved. these bits are reser ved and should not be written to. 7:0 setting these bits to 1 enables nesting of fiq interrupts. clearing these bits means no nesting or prioritization of fiqs is allowed. rev. d | page 90 o f 110
data sheet aduc7124/aduc7126 fiqvec register the fiq interrupt vector register, fiqvec, points to a memory a ddress containing a pointer to the interrupt service routine of the currently active fiq. this register should be read only when an fiq occurs and fiq interrupt nesting has been enabled by setting bit 1 of the irqconn register. name: fiqvec address: 0xff ff011c default value : 0x00000000 access: read only table 136 . fiqvec mmr bit descriptions bit type initial value description [31:23] r 0 always read as 0. [22:7] r/w 0 irqbase register value. [6:2] 0 highest priority source . this is a value between 0 and 27, representing the currently active interrupt source. the interrupts are listed in table 126 . for example, if the highest currently active fiq is timer2, then these bits are [00100 ]. [1:0] 0 reserved. fiqstan register if irqconn bit 1 is asserted and fiqvec is read, one of the fiqstan[7:0] bits is asserted. the bit that asserts depends on the priority of the fiq. if the fiq is of priority 0, bit 0 asserts, if priority 1, bit 1 as serts, and so forth. when a bit is set in this register all interrupts of that priority and lower are blocked. to clear a bit in this register, all bits of a higher priority must be cleared first. it is possible to clear only one bit at a time. for example , if this register is set to 0x09, then writing 0xff changes the register to 0x08 and writing 0xff a second time changes the register to 0x00. name: fiqstan address: 0xffff013c default value : 0x00000000 access: read/write table 137 . fiqstan mmr bit descriptions bit name description 31:8 reserved. these bits are reserved and should not be written to. 7:0 setting this bit to 1 enables nesting of fiq interrupts. clearing this bit means no nesting or prioritization of fiqs is a llowed. external interrupts and pla interrupts the aduc7124 / aduc7126 provide up to four external interrupt sources and two pla interrupt sources. these external interrupts can be individually configured as level or rising/falling edge triggered. to enable the external interrupt source or the pla interrupt source, the appropriate bit must first be set in the fiqen or i rqen register. to select the required edge or level to trigger on, the irqcone register must be appropriately configured. to properly clear an edge - based external irq interrupt or an edge - based pla interrupt, set the appropriate bit in the irqclre register . irqcone register name: irqcone address: 0xffff0034 default value : 0x00000000 access: read/write table 1 38 . irqcone mmr bit descriptions bit value name description [31:12] reserved. these bits are reserved and should n ot be written to. [11:10] 11 pla1src[1:0] pla irq1 triggers on falling edge. 10 pla irq1 triggers on rising edge. 01 pla irq1 triggers on low level. 00 pla irq1 triggers on high level. [9:8] 11 irq3src[1:0] external irq3 triggers on falling edge . 10 external irq3 triggers on rising edge. 01 external irq3 triggers on low level. 00 external irq3 triggers on high level. rev. d | page 91 of 110
aduc7124/aduc7126 data sheet bit value name description [7:6] 11 irq2src[1:0] external irq2 triggers on falling edge. 10 external irq2 triggers on rising edge. 01 external irq2 triggers on low level. 00 external irq2 triggers on high level. [5:4] 11 pla0src[1:0] pla irq0 triggers on falling edge. 10 pla irq0 triggers on rising edge. 01 pla irq0 triggers on low level. 00 pla irq0 triggers on high level. [3:2] 1 1 irq1src[1:0] external irq1 triggers on falling edge. 10 external irq1 triggers on rising edge. 01 external irq1 triggers on low level. 00 external irq1 triggers on high level. [1:0] 11 irq0src[1:0] external irq0 triggers on falling edge. 10 external irq0 triggers on rising edge. 01 external irq0 triggers on low level. 00 external irq0 triggers on high level. irqclre register name: irqclre address: 0xffff0038 default value : 0x00000000 access: write only table 139 . irqclre mmr bit descriptions bit name description [31:25] reserved. these bits are reserved and should not be written to. 24 pla1clri a 1 must be written to this bit in the pla irq1 interrupt service routine to clear an edge - triggered pla irq1 interrupt. 23 irq3clri a 1 must be written to this bit in the external irq3 interrupt service routine to clear an edge - triggered irq3 interrupt. 22 irq2clri a 1 must be written to this bit in the external irq2 interrupt service routine to clear an edge - t riggered irq2 interrupt. 21 pla0clri a 1 must be written to this bit in the pla irq0 interrupt service routine to clear an edge - triggered pla irq0 interrupt. 20 irq1clri a 1 must be written to this bit in the external irq1 interrupt service routine to cl ear an edge - triggered irq1 interrupt. [19:18] reserved. these bits are reserved and should not be written to. 17 irq0clri a 1 must be written to this bit in the external irq0 interrupt service routine to clear an edge triggered irq0 interrupt. [16:0] reserved. these bits are reserved and should not be written to. rev. d | page 92 o f 110
data sheet aduc7124/aduc7126 timers the aduc7124 / aduc7126 have four general - purpose timers/counters. ? timer0 ? timer1 ? timer2 or wake - up timer ? timer3 or watchdog timer these four timers in their normal mode of operation can be either free running or periodic. in free - running mode, the counter decreases from the maxi - mum value until ze ro scale is reached and starts again at the minimum value. it also increases from the minimum value until full scale is reached and starts again at the maximum value. in periodic mode, the counter decrements/increments from the value in the load register ( txld mmr) until zero/full scale is reached and starts again at the value stored in the load register. the timer interval is calculated as follows: if the timer is set to count down , then ( ) clock source prescaler txld interval = ( ) clock source prescaler txld fullscale interval = hr: min: sec: 1/128 format timer 1 and timer 2 have an hr: min: sec : hundreds format. to use the timer in hr: min: sec : hundreds format , the 32768 khz clock and prescaler o f 256 should be selected. the hundreds field does not represent milliseconds , but 1/128 of a second (256/32 768).the bits representing the h our, minute , and second are not consecutive in the register. this arrange - ment applies to t xld and txval when using the hr: min: sec : hundreds format as set in txcon[5:4]. see table 140 for more details. table 140 . hr: min: sec : hundreds format bit value description [ 31:24 ] 0 to 23 or 0 to 255 hours [ 23 :22 ] 0 reserved [ 21:16 ] 0 to 59 minutes [ 15:14 ] 0 reserved [ 13:8 ] 0 to 59 seconds 7 0 r eserved [ 6:0 ] 0 to 127 1/128 of second rev. d | page 93 of 110
aduc7124/aduc7126 data sheet timer0 (rtos timer) timer0 is a general - purpose, 16 - bit timer (count down) with a programmable prescaler. the prescaler s ource is the core clock frequency (hclk) and can be scaled by a factor of 1, 16, or 256. timer0 can be used to start adc conversions, as shown in the block diagram in figure 53. 09123-036 32.768khz oscillator uclk hclk prescaler 1, 16, or 256 16-bit down counter 16-bit load timer0 value timer0 irq adc conversion figure 53 . timer0 block diagram the timer0 interface consists of four mmrs: t0ld, t0val, t0con, and t0clri. t0ld register name: t0ld address: 0xffff0300 default value: 0x0000 access: read/write t0ld is a 16 - bit load register. t0val register name: t 0 va l add ress: 0xffff0304 default value: 0xffff access: read only t0val is a 16 - bit read - only register representing the current state of the counter. t0con register name: t0con address: 0xffff0308 default value: 0x0000 access: read/write t0con is the configu ration mmr described in table 141 . rev. d | page 94 o f 110
data sheet aduc7124/aduc7126 table 141 . t0con mmr bit descriptions bit value description [31:8] reserved. 7 timer0 enable bit. set by the user to enable timer0. cleared by t he user to disable timer0 by default. 6 timer0 mode. set by the user to operate in periodic mode. cleared by the user to operate in free - running mode. default mode. [5:4] clock select bits. 00 hclk. 01 uclk. 10 32.768 khz. 11 reserved. [3:2] prescale. 00 core clock/1. default value. 01 core clock/16. 10 core clock/256. 11 undefined. equivalent to 00. [1:0] reserved. t0clri register name: t0clri address: 0xffff030c default value: 0xff access: write only t0clri is an 8 - bit regist er. writing any value to this register clears the interrupt. timer1 (general - purpose timer) timer1 is a general - purpose, 32 - bit timer (count down or count up) with a programmable prescaler. the source can be the 32 khz external crystal, the undivided syste m, the core clock, or p1.1 (maximum frequency 41.78 mhz). this source can be scaled by a factor of 1, 16, 256, or 32,768. the counter can be formatted as a standard 32 - bit value or as hours: minutes: seconds: hundredths. timer1 has a capture register (t1c ap) that can be triggered by a selected irq source initial assertion. this feature can be used to determine the assertion of an event more accurately than the precision allowed by the rtos timer when the irq is serviced. timer1 can be used to start adc con versions. 09123-137 32khz oscillator hclk uclk p1.0 irq[19:0] prescaler 1, 16, 256, or 32,768 32-bit up/down counter 32-bit load timer1 value capture timer1 irq adc conversion figure 54 . timer1 block diagram the timer1 interface consists of five mmrs: t1ld, t1val, t1con, t1clri, and t1cap. t1ld register name: t1ld address: 0xffff0320 default value: 0x00000000 access: read/write t1ld is a 32- bit load register. t1val register name: t 1 va l address: 0xffff0324 default value: 0xffffffff access: read only t1val is a 32 - bit read - only register that represents the current state of the counter. t1con register name: t1con address: 0xffff0328 de fault value: 0x0000 access: read/write t1con is the configuration mmr described in table 142 . rev. d | page 95 of 110
aduc7124/aduc7126 data sheet table 142 . t1con mmr bit descriptions bit value description [31:18] reserved. 17 ev ent select bit. set by user to enable time capture of an event. cleared by the user to disable time capture of an event. [16:12] event select range, 0 to 25. these events are as described in table 126 . all ev ents are offset by two, that is, event 2 in table 126 becomes event 0 for the purposes of timer0. [11:9] clock select. 000 core clock (41 mhz/2 cd ). 001 32.768 khz. 010 uclk. 011 p1.0 raising edge trigge red. 8 count up. set by the user for timer1 to count up. cleared by the user for timer1 to count down by default. 7 timer1 enable bit. set by the user to enable timer1. cleared by the user to disable timer1 by default . 6 timer1 mode. set by the user to operate in periodic mode. cleared by the user to operate in free - running mode. default mode. [5:4] format. 00 binary. 01 reserved. 10 hr: min: sec: hundredths (23 hours to 0 hour). 11 hr: min: sec: hundredths (255 hours to 0 hour). [3:0 ] prescale. 0000 source clock/1. 0100 source clock/16. 1000 source clock/256. 1111 source clock/32,768. t1clri register name: t1clri address: 0xffff032c default value: 0xff access: write only t1clri is an 8 - bit register. writing any value to this register clears the timer1 interrupt. t1cap register name: t1cap address: 0xffff0330 default value: 0x00000000 access: read t1cap is a 32 - bit register. it holds the value contained in t1val when a particular event occurrs. this event must be selected in t1con. timer2 (wake - up timer) timer2 is a 32 - bit wake - up timer, count down or count up, with a programmable prescaler. the prescaler is clocked directly from one of four clock sources, including the core clock (default selec - tion), the interna l 32.768 khz oscillator, the external 32.768 khz watch crystal, or the pll undivided clock. the selected clock source can be scaled by a factor of 1, 16, 256, or 32,768. the wake - up timer continues to run when the core clock is disabled. this gives a minim um resolution of 22 ns when the core is operating at 41.78 mhz and with a prescaler of 1. capture of the current timer value is enabled if the timer2 interrupt is enabled via irqen[4] (see table 126). the counter can be formatted as a plain 32 - bit value or as hours: minutes: seconds: hundredths. timer2 reloads the value from t2ld either when timer2 overflows or immediately when t2clri is written. the timer2 interface consists of four mmrs, shown in table 143. table 143 . timer2 interface registers register description t2ld 32- bit register. holds 32 - bit unsigned integers. t2val 32- bit register. holds 32 - bit unsigned integers. this register is read only. t2clri 8 - bit register. writing any value to this register clears the timer2 interrupt. t2con configuration mmr. timer2 load registers name: t2ld address: 0xffff0340 default value: 0x00000 access: read/write t2ld is a 32 - bit register, which h olds the 32 - bit value that is loaded into the counter. rev. d | page 96 o f 110
data sheet aduc7124/aduc7126 timer2 clear register name: t2clri address: 0xffff034c default value: 0x00 access: write only this 8 - bit write - only mmr is written (with any value) by user code to refresh (reload) timer2. tim er2 value register name: t 2 va l address: 0xffff0344 default value: 0x0000 access: read only t2val is a 32 - bit register that holds the current value of timer2. timer2 control register name: t2con address: 0xffff0348 default value: 0x0000 access: read/ write this 32 - bit mmr configures the mode of operation for timer2. table 144 . t2con mmr bit descriptions bit value description [31:11] reserved. 10:9] clock source select. 00 external 32.768 khz watch crystal (default). 01 external 32.768 khz watch crystal. 10 internal 32.768 khz oscillator. 11 hclk. 8 count up. set by the user for timer2 to count up. cleared by the user for timer2 to count down (default). 7 timer2 enable bit. set by the user to enable timer2. cleared by the user to disable timer2 (default). 6 timer2 mode. set by the user to operate in periodic mode. cleared by the user to operate in free - running mode (default). [5:4] format. 00 binary (default). 01 reserved. 10 hr: min: sec: hundre dths (23 hours to 0 hours). 11 hr: min: sec: hundredths (255 hours to 0 hours). [3:0] prescaler. 0000 source clock/1 (default). 0100 source clock/16. 1000 source clock/256. 1111 source clock/32,768. rev. d | page 97 of 110
aduc7124/aduc7126 data sheet timer3 (watchdog time) timer3 has two mo des of operation: normal mode and watchdog mode. the watchdog timer is used to recover from an illegal software state. once enabled, it requires periodic servicing to prevent it from forcing a processor reset. normal mode timer3 in normal mode is identica l to timer0, except for the clock source and the count - up functionality. the clock source is 32 khz from the pll and can be scaled by a factor of 1, 16, or 256 (see figure 55). 09123-037 32.768khz prescaler 1, 16 or 256 16-bit up/down counter 16-bit load timer3 value watchdog reset timer3 irq figure 55 . timer3 block diagram watchdog mode watchdog mode is entered by setting bit 5 in the t3con mmr. timer3 decreases from the value present in the t3ld register until 0 is reached. t3ld is used as the timeout. the maximum timeout can be 512 sec using the presc aler/256 and full scale in t3ld. timer3 is clocked by the internal 32 khz crystal when operating in the watchdog mode. note that, to enter watchdog mode successfully, bit 5 in the t3con mmr must be set after writing to the t3ld mmr. if the timer reaches 0, a reset or an interrupt occurs, depending on bit 1 in the t3con register. to avoid reset or interrupt, any value must be written to t3clri before the expiration period. this reloads the counter with t3ld and begins a new timeout period. when watchdog mode is entered , t3ld and t3con are write - protected. these two registers cannot be modified until a reset clears the watchdog enable bit, which causes timer3 to exit watchdog mode. the timer3 interface consists of four mmrs: t3ld, t3val, t3con, and t3clri. t3l d register name: t3ld address: 0xffff0360 default value: 0x0000 access: read/write t3ld is a 16 - bit load register. t3val register name: t 3 va l address: 0xffff0364 default value: 0xffff access: read only t3val is a 16 - bit read - only register that rep resents the current state of the counter. t3con register name: t3con address: 0xffff0368 default value: 0x0000 access: read/write t3con is the configuration mmr described in table 145 . table 145 . t3con mmr bit descriptions bit value description [31:9] reserved. 8 count up. set by the user for timer3 to count up. cleared by the user for timer3 to count down by default. 7 timer3 enable bit. set by the user to enable timer3. clea red by the user to disable timer3 by default. 6 timer3 mode. set by the user to operate in periodic mode. cleared by the user to operate in free - running mode (default mode). 5 watchdog mode enable bit. set by the user to enable watchdog mode. cleare d by the user to disable watchdog mode by default. 4 secure clear bit. set by the user to use the secure clear option. cleared by the user to disable the secure clear option by default. [3:2] prescale. 00 source clock/1 by default. 01 source clock /16. 10 source clock/256. 11 undefined. equivalent to 00. 1 watchdog irq option bit. set by the user to produce an irq instead of a reset when the watchdog reaches 0. cleared by the user to disable the irq option. 0 reserved. rev. d | page 98 o f 110
data sheet aduc7124/aduc7126 rev. d | page 99 of 110 t3clri register name: t3clri address: 0xffff036c default value: 0x00 access: write only t3clri is an 8-bit register. writing any value to this register on successive occassions clears the timer3 interrupt in normal mode or resets a new timeout period in watchdog mode . note that the user must perform successive writes to this register to ensure resetting the timeout period. secure clear bit (watchdog mode only) the secure clear bit is provided for a higher level of protection. when set, a specific sequential value must be written to t3clri to avoid a watchdog reset. the value is a sequence generated by the 8-bit linear feedback shif t register (lfsr) polynomial = x 8 + x 6 + x 5 + x + 1, as shown in figure 56. 09123-038 clock qd 4 qd 5 qd 3 qd 7 qd 6 qd 2 qd 1 qd 0 figure 56. 8-bit lfsr the initial value or seed is written to t3clri before entering watchdog mode. after entering watchdog mode, a write to t3clri must match this expected value. if it matches, the lfsr is advanced to the next state when the counter reload occurs. if it fails to match the expected state, a reset is immediately generated, even if the count has not yet expired. the value 0x00 should not be used as an initial seed due to the properties of the polynomial. th e value 0x00 is always guaran- teed to force an immediate reset. the value of the lfsr cannot be read; it must be tracked/generated in software. example of a sequence: 1. enter initial seed, 0xaa, in t3clri before starting timer3 in watchdog mode. 2. enter 0xaa in t3clri; timer3 is reloaded. 3. enter 0x37 in t3clri; timer3 is reloaded. 4. enter 0x6e in t3clri; timer3 is reloaded. 5. enter 0x66. 0xdc was expected; the watchdog resets the chip. external memory interfacing the aduc7124 / aduc7126 feature an external memory interface. the external memory interface requires a larger number of pins. the xmcfg mmr must be set to 1 to use the external port. although 32-bit addresses are supported internally, only the lower 16 bits of the address are on external pins. the memory interface can address up to four 128 kb of asynchronous memory (sram or/and eeprom). the pins required for interfacing to an external memory are shown in table 146. table 146. external memory interfacing pins pin function ad[15:0] address/data bus. a16 extended addressing for 8-bit memory only. ms[3:0] memory select. ws write strobe. rs read strobe. ae address latch enable. bhe , ble byte write capability. there are four external memory regions available as described in table 147. associated with each region are the ms[3:0] pins. these signals allow access to the particular region of external memory. the size of each memory region can be 128 kb maxi- mum, 64 k 16 or 128 kb 8. to access 128 kb with an 8-bit memory, an extra address line (a16) is provided (see the example in figure 57). the four regions are configured independently. table 147. memory regions address start address end contents 0x10000000 0x1000ffff external memory 0 0x20000000 0x2000ffff external memory 1 0x30000000 0x3000ffff external memory 2 0x40000000 0x4000ffff external memory 3 each external memory region can be controlled through three mmrs: xmcfg, xmxcon, and xmxpar. 0 9123-039 latch aduc7126 ad15:ad0 a16 eeprom 64k 16-bit a0:a15 d0:d15 cs ram 128k 8-bit a0:a15 a16 d0:d7 cs we oe we oe ae ms0 ms1 ws rs figure 57. interfacing to external eeprom/ram
aduc7124/aduc7126 data sheet xmcfg register name: xmcfg address: 0xfffff000 default value: 0x00 access: read/write xmcfg is set to 1 to enable external memory access. this must be set to 1 before any port pins can function as external memory access pins. the port pins must also be individually enabled via the gpxcon mmr. table 148 . xmxcon registers name address default value access xm0con 0xfffff010 0x00 r/w xm1con 0xfffff014 0x00 r/w xm2 con 0xfffff018 0x00 r/w xm3con 0xfffff01c 0x00 r/w xmxcon are the control registers for each memory region. they allow the enabling/disabling of a memory region and control the data bus width of the memory region. table 149 . xmxco n mmr bit descriptions bit description 1 selects data bus width. set by the user to select a 16 - bit data bus. cleared by the user to select an 8 - bit data bus. 0 enables memory region. set by the user to enable memory region. cleared by the user to di sable the memory region. table 150 . xmxpar registers name address default value access xm0par 0xfffff020 0x70ff r/w xm1par 0xfffff024 0x70ff r/w xm2par 0xfffff028 0x70ff r/w xm3par 0xfffff02c 0x70ff r/w xmx pa r are registers that define the protocol used for accessing the external memory for each memory region. table 151 . xmxpar mmr bit descriptions bit description 15 enable byte write strobe. this bit is only used for two 8 - bit memory blocks sharing the same memory region. set by the user to gate the a0 output with the ws output. this allows byte write capability without using bhe and ble signals. cleared by user to use bhe and ble signals. [14:12] number of wait states on the address latch enable strobe. 11 reserved. 10 extra address hold time. set by the user to disable extra hold time. cleared by the user to enable one clock cycle of hold on the address i n read and write. 9 extra bus transition time on read. set by the user to disable extra bus transition time. cleared by the user to enable one extra clock before and after the read strobe ( rs ). 8 extra bus transition time on write. se t by the user to disable extra bus transition time. cleared by the user to enable one extra clock before and after the write strobe ( ws ). [7:4] number of write wait states. select the number of wait states added to the length of the ws pulse. 0x0 is 1 clock; 0xf is 16 clock cycles (default value). [3:0] number of read wait states. select the number of wait states added to the length of the rs pulse. 0x0 is 1 clock; 0xf is 16 clock cycles (default val ue). figure 58, figure 59, figure 60 , and figure 61 show the timing for a read cycle, a read cycle with address hold and bus turn cycles, a write cycle with address and write hold cycles, and a write cycle with wait sates, respectively. rev. d | page 100 o f 110
data sheet aduc7124/aduc7126 rev. d | page 101 of 110 09123-040 mclk ad[15:0] address data msx ae rs figure 58. external memory read cycle 09123-041 data address extra address hold time xmxpar (bit 10) bus turn out cycle (bit 9) bus turn out cycle (bit 9) mclk ad[15:0] msx ae rs figure 59. external memory read cycle with address hold and bus turn cycles
aduc7124/aduc7126 data sheet rev. d | page 102 of 110 09123-042 data address extra address hold time (bit 10) write hold address and data cycles (bit 8) write hold address and data cycles (bit 8) mclk ad[15:0] msx ae ws figure 60. external memory write cycle with address and write hold cycles 0 9123-043 data address 1 write strobe wait state (bit 7 to bit 4) 1 addr ess wait state (bit 14 to bit 12) mclk ad[15:0] msx ae ws figure 61. external memory write cycle with wait states
data sheet aduc7124/aduc7126 hardware design cons iderations power supplies the aduc7124 / aduc7126 operational power supply voltage range is 2.7 v to 3.6 v. separate analog and digital power supply pins (av dd and iov dd , respectively) allow av dd to be kept relatively free of noisy digital signals often present on the system iov dd line. in this mode, the part can also operate with split supplies; tha t is, it can use different voltage levels for each supply. for example, the system can be designed to operate with an iov dd voltage level of 3.3 v while the av dd level can be at 3 v or vice versa. a typical split supply configuration is shown in figure 62. 09123-044 aduc7124/ aduc7126 0.1f analog supply 10f av dd dacv dd gnd ref dacgnd agnd iov dd iognd 0.1f + ? digital supply 10f + ? figure 62 . external dual supply connections as an alternative to providing two separate power supplies, the user can reduce noise on av dd by placing a small series resistor and/or ferri te bead between av dd and iov dd and then decoupling av dd separately to ground. an example of this configuration is shown in figure 63 . with this configuration, other analog circuitry (such as op amps, voltage reference, or any other analog circuitry ) can be powered from the av dd supply line as well. 09123-145 aduc7124/ aduc7126 0.1f bead av dd agnd iov dd iov dd iov dd dgnd dgnd dgnd 0.1f digital supply analog supply 10f 10f + ? figure 63 . external single supply connections notice that in both fig ure 62 and figure 63 , a large value (10 f) reservoir capacitor sits on iov dd , and a separate 10 f capacitor sits on av dd . in addition, local small - value (0.1 f) capacitors are located at each av dd and iov dd pi n of the chip. as per standard design practice, be sure to include all of these capacitors and ensure that the smaller capacitors are close to each av dd pin with trace lengths as short as possible. connect the ground terminal of each of these capacitors di rectly to the underlying ground plane. finally, note that the analog and digital ground pins on the aduc7124 / aduc712 6 must be referenced to the same system ground reference point at all times. io v dd supply sensitivity the iov dd supply is sensitive to high frequency noise because it is the supply source for the internal oscillator and pll circuits. when the internal pll loses lock, the clock source is removed by a gating circuit from the cpu, and the arm7tdmi core stops executing code until the pll regains lock. this feature ensures that no flash interface timings or arm7tdmi timings are violated. typically, frequency no ise greater than 50 khz and 50 mv p - p on top of the supply causes the core to stop working. if decoupling values recommended in the power supplies section do not sufficiently dampen all noise sources below 50 m v on iov dd , a filter such as the one shown in figure 64 is recommended. aduc7124/ aduc7126 iov dd iognd 0.1f 0.1f digital supply 10f + ? 1h 09123-087 figure 64 . recommended iov dd supply filter linear voltage regulator the aduc7124 / aduc7126 require a single 3.3 v supply, but the core logic requires a 2.6 v supply. an on - chip linear regulator generates the 2.6 v from iov dd for the core logic. the lv dd pin is the 2.6 v supply for the core logic. an external compensation capacitor of 0.47 f must be connected between lv dd and dgnd (as close as possible to these pins) to act as a tank of charge as shown in figure 65. 09123-046 aduc7124/ aduc7126 0.47f lv dd dgnd figure 65 . voltage regulator connections the lv dd pin should not be used for any other chip. it is also recommended to use excellent power supply decoupli ng on iov dd to help improve line regulation performance of the on - chip voltage regulator. rev. d | page 103 of 110
aduc7124/aduc7126 data sheet rev. d | page 104 of 110 grounding and board layout recommendations as with all high resolution data converters, special attention must be paid to grounding and pc board layout of the aduc7124/ aduc7126 -based designs to achieve optimum performance from the adcs and dac. although the part has separate pins for analog and digital ground (agnd and iognd), the user must not tie these to two sepa- rate ground planes unless the two ground planes are connected very close to the part. this is illustrated in the simplified example shown in figure 66a. in systems where digital and analog ground planes are connected together somewhere else (at the power supply of the system, for example), the planes cannot be reconnected near the part because a ground loop results. in these cases, tie all the aduc7124/ aduc7126 agnd and iognd pins to the analog ground plane, as illustrated in figure 66b. in systems with only one ground plane, ensure that the digital and analog components are physically separated onto separate halves of the board so that digital return currents do not flow near analog circuitry (and vice versa). the aduc7124 / aduc7126 can then be placed between the digital and analog sections, as illustrated in figure 66c. 09123-047 a. place analog components here place digital components here agnd dgnd b. place analog components here place digital components here agnd dgnd c. place analog components here place digital components here dgnd figure 66. system grounding schemes in all of these scenarios, and in more complicated real-life applications, the users should pay particular attention to the flow of current from the supplies and back to ground. make sure the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. for example, do not power components on the analog side (as seen in figure 66b) with iov dd because that forces return currents from iov dd to flow through agnd. avoid digital currents flowing under analog circuitry, which can occur if a noisy digital chip is placed on the left half of the board (shown in figure 66c). if possible, avoid large discontinuities in the ground plane(s), such as those formed by a long trace on the same layer, because they force return signals to travel a longer path. in addition, make all connections to the ground plane directly, with little or no trace separating the pin from its via to ground. when connecting fast logic signals (rise/fall time < 5 ns) to any of the aduc7124/ aduc7126 digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than 5 ns at the input pins of the part. a value of 100 or 200 is usually sufficient to prevent high speed signals from coupling capacitively into the part and affecting the accuracy of adc conversions. clock oscillator the clock source for the aduc7124/ aduc7126 can be gener- ated by the internal pll or by an external clock input. to use the internal pll, connect a 32.768 khz parallel resonant crystal between xclki and xclko, and connect a capacitor from each pin to ground as shown in figure 67. the crystal allows the pll to lock correctly to give a frequency of 41.78 mhz. if no external crystal is present, the internal oscillator is used to give a typical frequency of 32.768 khz 3%. 09123-048 aduc7124/ aduc7126 to internal pll 12pf xclki 32.768khz 12pf xclko figure 67. external parallel resonant crystal connections to use an external source clock input instead of the pll (see figure 68), bit 1 and bit 0 of pllcon must be modified. the external clock uses p0.7 and xclk. 09123-049 aduc7124/ aduc7126 to frequency divider xclko xclki xclk external clock source figure 68. connecting an external clock source using an external clock source, the aduc7124/ aduc7126 specified operational clock speed range is 50 khz to 41.78 mhz 1%, which ensures correct operation of the analog peripherals and flash/ee.
data sheet aduc7124/aduc7126 rev. d | page 105 of 110 power-on reset operation an internal power-on reset (por) is implemented on the aduc7124/ aduc7126 . for lv dd below 2.40 v typical, the internal por holds the part in reset. as lv dd rises above 2.41 v, an internal timer times out for typically 128 ms before the part is released from reset. the user must ensure that the power supply, iov dd , reaches a stable 2.7 v minimum level by this time. likewise, on power-down, the internal por holds the part in reset until lv dd drops below 2.40 v. figure 69 illustrates the operation of the internal por in detail. 09123-050 io v dd 3.3 v 2.6v 2.41v typ 2.41v typ 128ms typ lv dd por mrst 0.12ms typ figure 69. internal power-on reset operation
aduc7124/aduc7126 data sheet rev. d | page 106 of 110 outline dimensions * compliant to jedec standards mo-220-vmmd-4 except for exposed pad dimension 0.25 min 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max seating plane pin 1 indicator * 4.85 4.70 sq 4.55 pin 1 indicator 0.30 0.23 0.18 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. top view exposed pad bottom view 9.10 9.00 sq 8.90 8.85 8.75 sq 8.65 06-13-2012-a figure 70. 64-lead frame chip scale package [lfcsp_vq] 9 mm x 9 mm body, very thin quad (cp-64-1) dimensions shown in millimeters compliant to jedec standards ms-026-bdd 051706-a 0.15 0.05 1.45 1.40 1.35 0.20 0.09 0.08 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 top view (pins down) 1 21 41 40 60 61 80 20 0.50 bsc lead pitch 0.27 0.22 0.17 1.60 max 0.75 0.60 0.45 view a pin 1 14.20 14.00 sq 13.80 12.20 12.00 sq 11.80 figure 71. 80-lead low profile quad flat package [lqfp] (st-80-1) dimensions shown in millimeters
data sheet aduc7124/aduc7126 ordering guide model 1 adc channels dac channels flash/ram gpio downloader temperature range package description package opti on ordering quantity aduc7 1 24bcpz126 10 2 126 kb/ 32 kb 30 uart ?40c to +125c 64 - lead lfcsp_vq cp - 64 - 1 260 aduc7 1 24bcpz126 - rl 10 2 126 kb/ 32 kb 30 uart ?40c to +125c 64 - lead lfcsp_vq cp - 64 - 1 2500 aduc7 1 26bstz126 12 4 126 kb/ 32 kb 40 uart ?40c to +12 5c 80 - lead lqfp st - 80 - 1 119 aduc7 1 26bstz126 - rl 12 4 126 kb/ 32 kb 40 uart ?40c to +125c 80 - lead lqfp st - 80 - 1 1000 aduc7 1 26bstz126i 12 4 126 kb/ 32 kb 40 i 2 c ?40c to +125c 80 - lead lqfp st - 80 - 1 119 aduc7 1 26bstz126irl 12 4 126 kb/ 32 kb 40 i 2 c ?40c to + 125c 80 - lead lqfp st - 80 - 1 1000 eval - aduc7124qspz aduc7124 quickstart development system eval - aduc7126qspz aduc7126 quickstart development system 1 z = rohs compliant part. rev. d | page 107 of 110
aduc 7124/aduc7126 data sheet notes rev. d | page 108 o f 110
data sheet aduc7124/aduc7126 notes rev. d | page 109 of 110
aduc 7124/aduc7126 data sheet notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2010 C 2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09123 - 0 - 10/14(d) rev. d | page 110 o f 110

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